參數(shù)資料
型號(hào): XRT83VL38IB-F
廠商: Exar Corporation
文件頁(yè)數(shù): 91/95頁(yè)
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標(biāo)準(zhǔn)包裝: 84
類(lèi)型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 8/8
規(guī)程: E1
電源電壓: 3.14 V ~ 3.47 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤(pán)
其它名稱: 1016-1481
XRT83VL38IB-F-ND
XRT83VL38
87
REV. 1.0.1
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 37 and
Figure 39 is described in Table 56.
FIGURE 36. RECEIVE CLOCK AND OUTPUT DATA TIMING
FIGURE 37. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
RCLK
R
RCLK
F
RCLK
RPOS
or
RNEG
R
DY
R
HO
ADDR[6:0]
DATA[7:0]
RD_DS
WR_R/W
RDY_DTACK
Valid Data for Readback
Data Available to W rite Into the LIU
READ OPERATIO N
W RITE O PERATIO N
t
0
t
0
t
1
t
3
t
2
t
4
Valid Address
t
5
t
5
ALE_AS
CS
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