參數(shù)資料
型號(hào)： XRT86VL34_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 11/63頁
文件大小： 402K
代理商： XRT86VL34_1
XRT86VL34
8
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxSERCLK0/
TxLINECLK0
TxSERCLK1/
TxLINECLK1
TxSERCLK2/
TxLINECLK2
TxSERCLK3/
TxLINECLK3
A12
E18
J15
V15
I/O
12
Transmit Serial Clock (TxSERCLKn)/Transmit Line Clock
(TxSERCLKn):
The exact function of these pins depends on the mode of operation
selected, as described below.
In Base-Rate Mode (1.544MHz/2.048MHz) - TxSERCLKn:
This clock signal is used by the transmit serial interface to latch the
contents on the TxSERn pins into the T1/E1 framer on the rising edge
of TxSERCLKn. These pins can be configured as input or output as
described below.
When TxSERCLKn is configured as Input:
These pins will be inputs if the TxSERCLK is chosen as the timing
source for the transmit framer. Users must provide a 1.544MHz clock
rate to this input pin for T1 mode of operation, and 2.048MHz clock
rate in E1 mode.
When TxSERCLKn is configured as Output:
These pins will be outputs if either the recovered line clock or the
MCLK PLL is chosen as the timing source for the T1/E1 transmit
framer. The transmit framer will output a 1.544MHz clock rate in T1
mode of operation, and a 2.048MHz clock rate in E1 mode.
DS1/E1 High-Speed Backplane Modes* - TxSERCLKn as INPUT
ONLY
In this mode, TxSERCLK is an optional clock signal input which is
used as the timing source for the transmit line interface, and is only
required if TxSERCLK is chosen as the timing source for the transmit
framer. If TxSERCLK is chosen as the timing source, system equip-
ment should provide 1.544MHz (For T1 mode) or 2.048MHz (For E1
mode) to the TxSERCLKn pins on each channel. TxSERCLK is not
required if either the recovered clock or MCLK PLL is chosen as the
timing source of the device.
High speed or multiplexed data is latched into the device using the
TxMSYNC/TxINCLK high-speed clock signal.
DS1 or E1 Framer Bypass Mode - TxLINECLKn
In this mode, TxSERCLKn is used as the transmit line clock (TxLI-
NECLK) to the LIU.
N
OTE
:
*High-speed backplane modes include (For T1/E1)
2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP,
H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz
Bit-multiplexed mode.
N
OTE
:
In DS1 high-speed modes, the DS-0 data is mapped into an
E1 frame by ignoring every fourth time slot (don’t care).
N
OTE
:
These 8 pins are internally pulled “High” for each channel.
TRANSMIT SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
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