參數(shù)資料
型號： XRT86VL34_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 20/63頁
文件大?。?/td> 402K
代理商： XRT86VL34_1
XRT86VL34
17
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
RECEIVE OVERHEAD INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
RxOH0
RxOH1
RxOH2
RxOH3
C11
B16
K15
P18
O
8
Receive Overhead Output (RxOHn):
These pins function as the Receive Overhead output, or
Receive Signaling Output depending on the receive framer
configuration, as described below.
DS1 Mode
If the RxOH pins have been configured as the destination for
the Data Link bits within an inbound DS1 frame, datalink bits
will be output to the RxOHn pins at either 2kHz or 4kHz
depending on the Receive datalink bandwidth selected.
(Register 0xn10C).
If configured appropriately, signaling information in the
receive signaling array registers (Registers 0xn500-0xn51F)
can also be output to the RxOHn output pins.
E1 Mode
These output pins will always output the contents of the
National Bits (Sa4 through Sa8) if these Sa bits have been
configured to carry Data Link information (Register 0xn10C).
The Receive Overhead Output Interface will provide a clock
edge on RxOHCLKn for each Sa bit carrying Data Link infor-
mation.
If configured appropriately, signaling information in the
receive signaling array registers (Registers 0xn500-0xn51F)
can also be output to the RxOHn output pins.
RxOHCLK0
RxOHCLK1
RxOHCLK2
RxOHCLK3
A9
D17
K17
R16
O
8
Receive Overhead Clock Output (RxOHCLKn):
This pin functions as an overhead output clock signal for the
receive overhead interface, and its function is explained
below.
DS1 Mode
If the RxOH pins have been configured to be the destination
for Datalink bits, the DS1 transmit framer will output a clock
edge for each Data Link Bit. In DS1 ESF mode, the RxO-
HCLK can either be a 2kHz or 4kHz output signal depending
on the selection of Data Link Bandwidth (Register 0xn10C).
Data Link Equipment can clock out datalink bits on the
RxOHn pin using this clock signal.
E1 Mode
The E1 receive framer provides a clock edge for each
National Bit (Sa bits) that is configured to carry data link infor-
mation.
Data Link Equipment can clock out datalink bits on the
RxOHn pin using this clock signal.
相關(guān)PDF資料
PDF描述
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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