參數(shù)資料
型號(hào): XRT86VL34_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 31/63頁
文件大?。?/td> 402K
代理商: XRT86VL34_1
XRT86VL34
28
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT LINE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
D
ESCRIPTION
TTIP0
TTIP1
TTIP2
TTIP3
E4
G4
J4
L4
O
Transmit Positive Analog Output (TTIPn):
TTIP is the positive differential output to the line interface. This output pin,
along with the corresponding TRING output pin, function as the Transmit DS1/
E1 output signal drivers for the XRT86VL34 device.
The user is expected to connect this signal and the corresponding TRING out-
put signal to a 1:2 step up transformer for proper operation.
This output pin will be tri-stated whenever the user sets the “TxON” input pin
or register bit (0xnF02, bit 3) to “0”.
N
OTE
:
This pin should have a series line capacitor of 0.68
μ
F for DC blocking
purposes.
TRING0
TRING1
TRING2
TRING3
F4
H4
K4
M4
O
Transmit Negative Analog Output (TRINGn):
TRING is the negative differential output to the line interface. This output pin,
along with the corresponding TTIP output pin, function as the Transmit DS1/
E1 output signal drivers for the XRT86VL34 device.
The user is expected to connect this signal and the corresponding TRING out-
put signal to a 1:2 step up transformer for proper operation.
N
OTE
:
This output pin will be tri-stated whenever the user sets the “TxON”
input pin or register bit (0xnF02, bit 3) to “0”.
TxON
N1
I
Transmitter On
This input pin permits the user to either enable or disable the Transmit Output
Driver within the Transmit DS1/E1 LIU Block. If the TxON pin is pulled “Low”,
all 8 Channels are tri-stated. When this pin is pulled ‘High’, turning on or off the
transmitters will be determined by the appropriate channel registers (address
0x0Fn2, bit 3)
LOW
= Disables the Transmit Output Driver within the Transmit DS1/E1 LIU
Block. In this setting, the TTIP and TRING output pins of all 8 channels will be
tri-stated.
HIGH
= Enables the Transmit Output Driver within the Transmit DS1/E1 LIU
Block. In this setting, the corresponding TTIP and TRING output pins will be
enabled or disabled by programming the appropriate channel register.
(address 0x0Fn2, bit 3)
N
OTE
:
Whenever the transmitters are turned off, the TTIP and TRING output
pins will be tri-stated.
TIMING INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
MCLKIN
A4
I
-
Master Clock Input:
This pin is used to provide the timing reference for the internal
master clock of the device. The frequency of this clock is pro-
grammable from 8kHz to 16.384MHz in register 0x0FE9.
E1MCLKnOUT
A3
O
12
LIU E1 Output Clock Reference
This output pin is defaulted to 2.048MHz, but can be programmed
to 4.096MHz, 8.192MHz, or 16.384MHz in register 0x0FE4.
相關(guān)PDF資料
PDF描述
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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