參數(shù)資料
型號: XRT86VL34_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 26/63頁
文件大?。?/td> 402K
代理商: XRT86VL34_1
XRT86VL34
23
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
RxCHN0_1/
RxFrTD0
RxCHN1_1/
RxFrTD1
RxCHN2_1/
RxFrTD2
RxCHN13_1/
RxFrTD3
C9
B15
G15
V18
O
8
Receive Time Slot Octet Identifier Output Bit 1 (RxCHNn_1)
/ Receive Serial Fractional Output (RxFrTDn):
The exact function of these pins depends on whether or not the
receive framer enables the receive fractional/signaling inter-
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_1:
These output pins (RxCHNn_4 through RxCHNn_0) reflect the
five-bit binary value of the current time slot being output by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the five output pins of each channel to identify
the time slot being output on these pins. RxCHNn_1 indicates
Bit 1 of the time slot channel being output.
If receive fractional/signaling interface is enabled -
RxFrTDn:
These pins are used as the fractional data output pins to output
fractional DS1/E1 payload data within an inbound DS1/E1
frame. In this mode, system equipment can use either RxCH-
CLK or RxSERCLK to clock out fractional DS1/E1 payload data
depending on the framer configuration.
N
OTE
:
Receive Fractional/Signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 to ‘1’.
RxCHN0_2/
RxCHN0
RxCHN1_2/
RxCHN1
RxCHN2_2/
RxCHN2
RxCHN3_2/
RxCHN3
B9
A17
K18
T15
O
8
Receive Time Slot Octet Identifier Output-Bit 2 (RxCHNn_2)
/ Receive Time Slot Identifier Serial Output (RxCHNn):
The exact function of these pins depends on whether or not the
receive framer enables the receive fractional/signaling inter-
face, as described below:
If receive fractional/signaling interface is disabled -
RxCHNn_2:
These output pins (RxCHNn_4 through RxCHNn_0) reflect the
five-bit binary value of the current time slot being output by the
receive serial interface. System equipment can use the RxCH-
CLKn to sample the five output pins of each channel to identify
the time slot being output on these pins. RxCHNn_2 indicates
Bit 2 of the time slot channel being output.
If receive fractional/signaling interface is enabled -
RxCHNn
These pins serially output the five-bit binary value of the time
slot being output by the receive serial interface.
N
OTE
:
Receive Fractional/Signaling interface can be enabled
by programming to bit 4 - RxFr1544/RxFr2048 bit from
register 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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