參數(shù)資料
型號(hào)： XRT86VL34_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 37/63頁(yè)
文件大?。?/td> 402K
代理商： XRT86VL34_1
XRT86VL34
34
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RDY
T3
O
12
Ready/Data Transfer Acknowledge Output:
The exact behavior of this pin depends upon the type of Micro-
processor/Microcontroller the XRT86VL34 has been configured
to operate in, as defined by the PTYPE[2:0] pins.
Intel Asynchronous Mode - RDY* - Ready Output
Tis output pin will function as the “active-low” READY output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic low level, ONLY
when the Microprocessor Interface is ready to complete or ter-
minate the current READ or WRITE cycle. Once the Micropro-
cessor has determined that this input pin has toggled to the
logic “l(fā)ow” level, then it is now safe for it to move on and exe-
cute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Inter-
face block is holding this output pin at a logic “high” level, then
the Microprocessor is expected to extend this READ or WRITE
cycle, until it detects this output pin being toggled to the logic
low level.
Motorola Asynchronous Mode - DTACK* - Data Transfer
Acknowledge Output
Tis output pin will function as the “active-low” DTACK output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic low level, ONLY
when the Microprocessor Interface is ready to complete or ter-
minate the current READ or WRITE cycle. Once the Micropro-
cessor has determined that this input pin has toggled to the
logic “l(fā)ow” level, then it is now safe for it to move on and exe-
cute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Inter-
face block is holding this output pin at a logic “high” level, then
the Microprocessor is expected to extend this READ or WRITE
cycle, until it detects this output pin being toggled to the logic
low level.
Power PC 403 Mode - RDY Ready Output:
This output pin will function as the “active-high” READY output.
During a READ or WRITE cycle, the Microprocessor Interface
block will toggle this output pin to the logic high level, ONLY
when the Microprocessor Interface is ready to complete or ter-
minate the current READ or WRITE cycle. Once the Micropro-
cessor has sampled this signal being at the logic “high” level
upon the rising edge of PCLK, then it is now safe for it to move
on and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Inter-
face block is holding this output pin at a logic “l(fā)ow” level, then
the Microprocessor is expected to extend this READ or WRITE
cycle, until it samples this output pin being at the logic low
level.
N
OTE
:
The Microprocessor Interface will update the state of
this output pin upon the rising edge of PCLK.
MICROPROCESSOR INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL34ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4 IND FULL DPLX FIFO TWO-FRAME, CAS, CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL34IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
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