參數(shù)資料
型號(hào): XRT86VL34_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 29/63頁(yè)
文件大小: 402K
代理商: XRT86VL34_1
XRT86VL34
26
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE LINE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
RTIP0
RTIP1
RTIP2
RTIP3
E1
G1
J1
L1
I
-
Receive Positive Analog Input (RTIPn):
RTIP is the positive differential input from the line interface. This
input pin, along with the RRING input pin, functions as the “Receive
DS1/E1 Line Signal” input for the XRT86VL34 device.
The user is expected to connect this signal and the RRING input
signal to a 1:1 transformer for proper operation. The center tap of
the receive transformer should have a bypass capacitor of 0.1
μ
F to
ground (Chip Side) to improve long haul application receive capa-
bilities.
RRING0
RRING1
RRING2
RRING3
F1
H1
K1
M1
I
-
Receive Negative Analog Input (RRINGn):
RRING is the negative differential input from the line interface. This
input pin, along with the RTIP input pin, functions as the “Receive
DS1/E1 Line Signal” input for the XRT86VL34 device.
The user is expected to connect this signal and the RTIP input sig-
nal to a 1:1 transformer for proper operation. The center tap of the
receive transformer should have a bypass capacitor of 0.1
μ
F to
ground (Chip Side) to improve long haul application receive capa-
bilities.
RxLOS_0
RxLOS_1
RxLOS_2
RxLOS_3
B7
C18
G16
U18
O
4
Receive Loss of Signal Output Indicator (RLOSn):
The XRT86VL34 device will assert this output pin (i.e., toggle it
“high”) anytime (and for the duration that) the Receive DS1/E1
Framer or LIU block declares the LOS defect condition.
Conversely, the XRT86VL34 device will tri-state this output pin any-
time (and for the duration that) the Receive DS1/E1 Framer or LIU
block is NOT declaring the LOS defect condition.
N
OTES
:
1.
This output pin will toggle "high" (to denote that LOS is
being declared) whenever either the Receive DS1/E1
Framer or the Receive DS1/E1 LIU block (associated wtih
Channel N) declares the LOS defect condition. In other
words, the state of this output pin is a logical OR of the
Framer LOS and the LIU LOS conditions.
2.
Since the XRT86VL34 device tri-states this output pin
(anytime the channel is not declaring the LOS defect
condition). Therefore, the user MUST connect a "pull-
down" resistor (ranging from 1K to 10K) to each RxLOS
output pin, in order to pull this output pin to the logic
"LOW" condition, whenever the Channel is NOT declaring
the LOS defect condition.
相關(guān)PDF資料
PDF描述
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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