參數(shù)資料
型號： XRT91L80IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PBGA196
封裝： 12 X 12 MM, STBGA-196
文件頁數(shù)： 11/45頁
文件大?。?/td> 359K
代理商： XRT91L80IB
xr
REV. P1.1.0
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80
9
RECEIVER SECTION
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
RXDO0P
RXDO0N
RXDO1P
RXDO1N
RXDO2P
RXDO2N
RXDO3P
RXDO3N
LVDS
O
E13
F13
C14
D14
C13
D13
A14
B14
Receive Parallel Data Output
622Mbps 4-bit parallel receive data output is updated simulta-
neously on the rising edge of the RXPCLKOP/N output. The 4-
bit parallel interface is de-multiplexed from the receive serial
data input MSB first (RXDO3P/N).
N
OTE
:
The XRT91L80 can output 666.51 Mbps 4-bit parallel
receive data output for Forward Error Correction (FEC)
Applications.
RXPCLKOP
RXPCLKON
LVDS
O
E14
F14
Receive Parallel Clock Output
622.08 MHz parallel clock output used to update the 4-bit paral-
lel receive data output RXDO[3:0]P/N at the rising edge of this
clock..
N
OTE
:
The XRT91L80 can output a 666.51 MHz receive clock
output for Forward Error Correction (FEC).
DISRD
LVTTL
LVCMOS
I
C12
Parallel Receive Data Output Disable
This pin is used to disable the RXDO[3:0]P/N parallel receive
data output bus asynchronously.
"Low" = Normal Mode
"High" = Forces RXDO[3:0]P/N to a logic state "0"
This pin is provided with an internal pull-down.
RXIP
RXIN
CMLDIFF
I
C1
D1
Receive Serial Data Input
The receive serial data stream of 2.488 Gbps is applied to
these input pins. In Forward Error Correction, the receive
serial data stream is 2.666 Gbps.
XRES1P
XRES1N
-
I
G1
F1
External LVDS Biasing Resistors
A 402
resistor with +/-1% tolerance should be placed across
these 2 pins for proper biasing.
RXCLKO16P
RXCLKO16N
LVDS
O
A6
A7
Auxiliary Clock Output (155.52/166.63 MHz)
155.52/166.63 MHz auxiliary clock derived from divide-by-16
CDR recovered clock.
LOCKDET_CDR
LVCMOS
O
C7
CDR Lock Detect
This pin is used to monitor the lock condition of the clock and
data recovery unit.
"Low" = CDR Out of Lock
"High" = CDR Locked
SDEXT
LVTTL,
LVCMOS
I
B5
Signal Detect Input from Optical Module
Hardware Mode
When inactive, it will immediately declare a
Loss of Signal Detect (LOSD) condition and assert LOSDET
output pin and control the activity of the RXDO[3:0]P/N parallel
data output based on LOSDMUTE pin setting.
Host Mode
In addition to asserting LOSDET output pin, it will
update the LOSD condition on the registers and control the
activity of the RXDO[3:0]P/N parallel data output based on
LOSDMUTE register bit setting.
"Active" = Normal Operation
"Inactive" = LOSD Condition (SDEXT detects signal absence)
This pin is provided with an internal pull-down.
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相關代理商/技術參數(shù)
參數(shù)描述
XRT91L80IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L81 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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