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參數(shù)資料
| 型號： | XRT91L80IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | TRANSCEIVER, PBGA196 |
| 封裝： | 12 X 12 MM, STBGA-196 |
| 文件頁數(shù)： | 37/45頁 |
| 文件大小： | 359K |
| 代理商： | XRT91L80IB |
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xr
REV. P1.1.0
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80
35
T
ABLE
15: M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
T
ABLE
16: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
C
ONFIGURATION
1 C
ONTROL
R
EGISTER
(0
X
04
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
X
D6
POLARITY
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
R/W
0
D5
LOOPTM_JA
Loop Timing With Jitter Attenuation
The LOOPTM_JA bit must be set to "1" in order to select the recov-
ered receive clock as the reference source for the de-jitter PLL.
"0" = Disabled
"1" = Loop timing with de-jitter PLL Activated
R/W
0
D4
LOOPTM_
NOJA
Loop Timing With No Jitter Attenuation
When the loop timing mode is activated, the external local refer-
ence clock input to the CMU is replaced with the 1/16th or 1/32nd
of the high-speed recovered receive clock coming from the CDR.
"0" = Disabled
"1" = Loop timing Activated
R/W
0
D3
LOSDMUTE
Parallel Receive Data Output Mute Upon LOSD
If this bit is set to "1", the receive data output will automatically be
forced to a logic state of "0" when an LOSD condition occurs.
"0" = Disabled
"1" = Mute RXDO[3:0]P/N Data Upon LOSD Condition
R/W
0
D2
DISRD
Parallel Receive Data Output Disable
This bit is used to disable the RXDO[3:0]P/N parallel receive data
output bus asynchronously.
"0" = Normal Mode
"1" = Forces RXDO[3:0]P/N to a logic state "0"
R/W
0
D1
Reserved
Reserved - Set to 0
R/W
0
D0
VCXOLKEN
De-Jitter PLL Lock Detect Enable
This bit enables the VCXO_INP/N lock detect circuit to be active.
"0" = VCXO Lock Detect Disabled
"1" = VCXO Lock Detect Enabled
R/W
0
D
IAGNOSTIC
C
ONTROL
R
EGISTER
(0
X
05
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
X
D6
Reserved
This Register Bit is Not Used
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L81 | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT94L31_07 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L80IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L81 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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