參數(shù)資料
型號(hào)： XRT91L80IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PBGA196
封裝： 12 X 12 MM, STBGA-196
文件頁(yè)數(shù)： 17/45頁(yè)
文件大?。?/td> 359K
代理商： XRT91L80IB
xr
REV. P1.1.0
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80
15
2.2
The clock and data recovery unit accepts the high speed NRZ serial data from the differential CML receiver
and generates a clock that is the same frequency as the incoming data. The clock recovery utilizes the
REFCLKP/N to train and monitor its clock recovery PLL. Initially upon startup, the PLL locks to the local
reference clock within ±500 ppm. Once this is achieved, the PLL then attempts to lock onto the incoming
receive data stream. Whenever the recovered clock frequency deviates from the local reference clock
frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock back onto the
local reference clock. When this condition occurs the PLL will declare Loss of Lock and the LOCKDET_CDR
signal will be pulled "Low." Whenever a Loss of Lock/Loss of Signal Detection (LOSD) event occurs, the CDR
will continue to supply a receive clock (based on the local reference clock) to the upstream framer device. A
Loss of Lock condition will also be declared when the external SDEXT becomes inactive. When the SDEXT is
de-asserted by the optical module and LOSDMUTE is enabled, receive parallel data output will be forced to a
logic zero state for the entire duration that a LOSD condition is detected. This acts as a receive data mute upon
LOSD function to prevent random noise from being misinterpreted as valid incoming data. When SDEXT
becomes active and the recovered clock is determined to be within ±500 ppm accuracy with respect to the
local reference source, the clock recovery PLL will switch and lock back onto the incoming receive data stream
and the lock detect output (LOCKDET_CDR) will go active. Table 3 specifies the Clock and Data Recovery
Unit performance characteristics.
T
ABLE
3: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
Receive Clock and Data Recovery
Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter.
1
Required to meet SONET output frequency stability requirements.
2.3
XRT91L80 supports external Signal Detection (SDEXT). The external Signal Detect function is supported by
the SDEXT input. This input is coming from the optical module through an output usually called “SD” or “FLAG”
which indicates the lack or presence of optical power. Depending on the manufacturer of these devices, the
polarity of this signal can be either active "Low" or active "High." The SDEXT and POLARITY inputs are
Exclusive OR’ed to generate the external LOSDET signal, internal Loss of Signal Detect (LOSD) declaration
and Mute upon LOSD control signal. Whenever an external SD is absent, the XRT91L80 will automatically
output a high level signal on the LOSDET output pin as well as update the control registers whenever the host
mode serial microprocessor interface feature is active. If LOSDMUTE is enabled, it will force the receive
parallel data output to a logic state "0" for the entire duration that a LOSD condition is declared. This acts as a
receive data mute upon LOSD function to prevent random noise from being misinterpreted as valid incoming
data. Table 4 specifies SDEXT declaration polarity settings.
External Signal Detection
N
AME
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
REF
DUTY
Reference clock duty cycle
45
55
%
REF
TOL
Reference clock frequency tolerance
1
-20
+20
ppm
OCLK
JIT
Clock output jitter generation with 77.76 MHz reference clock
3.5
5.0
mUI
rms
OCLK
JIT
Clock output jitter generation with 155.52 MHz reference clock
3.7
5.0
mUI
rms
TOL
JIT
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
0.4
0.7
UI
OCLK
FREQ
Frequency output
2.488
2.667
GHz
OCLK
DUTY
Clock output duty cycle
45
55
%
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XRT91L80IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L81 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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