參數(shù)資料
型號(hào): XRT91L80IB
廠商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 12 X 12 MM, STBGA-196
文件頁(yè)數(shù): 31/45頁(yè)
文件大小: 359K
代理商: XRT91L80IB
xr
REV. P1.1.0
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80
29
5.0
The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the
transceiver. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the
registers, monitor the transceiver via an interrupt pin, and reset the transceiver to its default configuration by
pulling reset "Low" for more than 10ms. A simplified block diagram of the Serial Microprocessor is shown in
Figure 24.
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
SERIAL MICROPROCESSOR INTERFACE BLOCK
5.1
The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor
samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 16
bits of serial data have been sampled. A timing diagram of the Serial Microprocessor is shown in Figure 25.
F
IGURE
25. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
S
ERIAL
T
IMING
I
NFORMATION
N
OTE
:
The serial microprocessor interface does
NOT
support "burst write" or "burst read" operations. Chip Select (active
"Low")
must be de-asserted
at the end of every single write or single read operation.
Serial
Microprocessor
Interface
CS
SDI
SCLK
SDO
INT
RESET
HW/Host
CS
SDI
SCLK
SDO
1
2
10
9
8
7
6
5
4
3
11
16
15
13
14
12
R/W
A0
A1
A2
A3
A4
A5
X
D0
D1
D7
D6
D5
D4
D3
D2
D0
D1
D7
D6
D5
D4
D3
D2
High-Z
High-Z
25nS
50nS
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