參數(shù)資料
型號(hào)： XRT91L81
廠商： Exar Corporation
英文描述： 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： 2.488/2.666GBPS OC-48/STM-16的SONET / SDH收發(fā)器
文件頁(yè)數(shù)： 10/40頁(yè)
文件大?。?/td> 264K
代理商： XRT91L81
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
8
LOCKDET_CMU
LVTTL
O
N2
CMU Lock
This pin is used to monitor the lock condition of the clock multi-
plier unit.
"Low" = CMU out of Lock
"High" = CMU Locked
OVERFLOW
LVTTL
O
M13
Transmit FIFO Overflow
This pin is used to monitor the transmit FIFO status.
"Low" = Normal Status
"High" = Overflow Condition
FIFO_RST
LVTTL
I
N13
FIFO Control Reset
Hardware Mode
FIFO_RST should be held "High" for 10 cycles
of TXCLK during power-up in order to flush out the FIFO. Upon
an interrupt indication that the FIFO has an overflow condition,
this pin is used to reset or flush out the FIFO.
N
OTE
:
To automaically reset the FIFO, see Pin
FIFO_AUTORST.
FIFO_AUTORST
LVTTL
I
N12
Automatic FIFO Reset
Hardware Mode
If this pin is set "High", the OC-48 transceiver
will automatically flush the FIFO upon an overflow condition.
Upon power-up, the FIFO should be manually reset by pulling
FIFO_RST "High" for 10 cycles of TXCLK.
"Low" = Manual FIFO reset required for overflow conditions
"High" = Automatically resets FIFO upon overflow detection
RECEIVER SECTION
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
RXD0P
RXD0N
RXD1P
RXD1N
RXD2P
RXD2N
RXD3P
RXD3N
LVDS
O
E13
F13
C14
D14
C13
D13
A14
B14
Receive Parallel Data Output
622Mbps 4-bit parallel receive output data is updated simulta-
neously on the rising edge of the RXCLK output. The 4-bit par-
allel interface is de-multiplexed from the receive serial input
data MSB first (RXD3P/N).
N
OTE
:
The XRT91L81 can output 666Mbps 4-bit parallel
receive output data for Forward Error Correction (FEC)
Applications.
RXCLKP
RXCLKN
LVDS
O
E14
F14
Receive Output Clock
622MHz output clock reference for the 4-bit parallel receive
output data RXDP/N[3:0].
N
OTE
:
The XRT91L81 can output a 666MHz receive output
clock for Forward Error Correction (FEC).
TRIRXD
LVTTL
I
C12
Tri-State Receive Parallel Data Output
Hardware Mode
This pin is used to control the activity of the 4-
bit parallel receive output bus and its reference clock.
"Low" = Normal Mode
"High" = Tri-State RXDP/N[3:0] and RXCLK
TRANSMITTER SECTION
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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