參數(shù)資料
型號： XRT91L81
廠商： Exar Corporation
英文描述： 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： 2.488/2.666GBPS OC-48/STM-16的SONET / SDH收發(fā)器
文件頁數(shù)： 4/40頁
文件大?。?/td> 264K
代理商： XRT91L81
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT91L81 ............................................................................................................................... 1
FEATURES
......................................................................................................................................................2
PRODUCT ORDERING INFORMATION..................................................................................................2
T
ABLE
1: 196 BGA P
INOUT
OF
THE XRT91L81 (T
OP
V
IEW
) ........................................................................................................... 3
T
ABLE
OF
C
ONTENTS
............................................................................................................I
PIN DESCRIPTIONS ..........................................................................................................4
S
ERIAL
M
ICROPROCESSOR
INTERFACE
............................................................................................................4
H
ARDWARE
CONTROL
.....................................................................................................................................5
T
RANSMITTER
S
ECTION
..................................................................................................................................6
RECEIVER
SECTION
.........................................................................................................................................8
P
OWER
AND
G
ROUND
..................................................................................................................................10
N
O
C
ONNECTS
.............................................................................................................................................11
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12
1.2 INPUT CLOCK REFERENCE ......................................................................................................................... 12
1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 12
T
ABLE
2: R
EFERENCE
F
REQUENCY
O
PTIONS
(N
ORMAL
M
ODE
/FEC) ................................................................................................ 12
F
IGURE
2. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
F
ORWARD
E
RROR
C
ORRECTION
.................................................................................... 12
2.0 RECEIVE SECTION .............................................................................................................................13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
F
IGURE
3. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 13
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 14
2.3 LOSS OF SIGNAL .......................................................................................................................................... 14
2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 14
F
IGURE
4. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
SIPO ........................................................................................................................... 14
2.5 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 15
2.6 RECEIVE PARALLEL OUTPUT DATA TIMING ............................................................................................ 15
F
IGURE
6. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
.............................................................................................................................. 15
T
ABLE
3: R
ECEIVE
P
ARALLEL
O
UTPUT
D
ATA
T
IMING
S
PECIFICATIONS
.............................................................................................. 15
2.7 DISABLE RECEIVE OUTPUT DATA UPON LOS .......................................................................................... 15
2.8 TRI-STATE RECEIVE OUTPUT DATA .......................................................................................................... 15
F
IGURE
5. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 15
3.0 TRANSMIT SECTION ..........................................................................................................................16
3.1 TRANSMIT PARALLEL INTERFACE ............................................................................................................ 16
F
IGURE
7. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................... 16
3.2 TRANSMIT PARALLEL INPUT DATA TIMING .............................................................................................. 17
F
IGURE
8. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
................................................................................................................................ 17
T
ABLE
4: T
RANSMIT
P
ARALLEL
I
NPUT
D
ATA
T
IMING
S
PECIFICATIONS
............................................................................................... 17
3.3 TRANSMIT FIFO ............................................................................................................................................. 17
3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 17
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 18
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 18
F
IGURE
9. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO ........................................................................................................................... 18
F
IGURE
10. T
RANSMIT
FIFO
AND
S
YSTEM
I
NTERFACE
.................................................................................................................... 19
3.7 LOOP TIMING AND CLOCK CONTROL ........................................................................................................ 20
T
ABLE
5: L
OOP
TIMING
AND
REFERENCE
DE
-
JITTER
CONFIGURATIONS
.............................................................................................. 20
3.8 EXTERNAL LOOP FILTER ............................................................................................................................. 21
F
IGURE
12. S
IMPLIFIED
D
IAGRAM
OF
THE
E
XTERNAL
L
OOP
F
ILTER
.................................................................................................. 21
F
IGURE
11. L
OOP
T
IMING
M
ODE
U
SING
AN
E
XTERNAL
C
LEANUP
VCXO.......................................................................................... 21
3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 22
F
IGURE
13. T
RANSMIT
S
ERIAL
O
UTPUT
I
NTERFACE
......................................................................................................................... 22
4.0 DIAGNOSTIC FEATURES ...................................................................................................................23
4.1 SERIAL REMOTE LOOPBACK ...................................................................................................................... 23
4.2 PARALLEL REMOTE LOOPBACK ................................................................................................................ 23
F
IGURE
14. S
ERIAL
R
EMOTE
L
OOPBACK
......................................................................................................................................... 23
相關(guān)PDF資料
PDF描述
XRT91L81IB 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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