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參數資料
| 型號： | XRT91L81 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | 2.488/2.666GBPS OC-48/STM-16的SONET / SDH收發(fā)器 |
| 文件頁數： | 19/40頁 |
| 文件大?。?/td> | 264K |
| 代理商： | XRT91L81 |
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XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
REV. P1.0.3
17
3.2
When applying parallel input data to the transmitter, the setup and hold times should be followed as shown in
Figure 8 and Table 4.
F
IGURE
8. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
Transmit Parallel Input Data Timing
T
ABLE
4: T
RANSMIT
P
ARALLEL
I
NPUT
D
ATA
T
IMING
S
PECIFICATIONS
3.3
The Parallel Interface also includes a 4x9 FIFO that can be used to eliminate difficult timing issues between the
input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to tolerate an
arbitrary amount of delay and jitter between TXCLKOP/N and TXCLKIP/N. The FIFO can be initialized when
FIFO_RESET is asserted and held low for 10 cycles of the TXCLKO clock. Once the FIFO is centered, the
delay between TXCLKO and TXCLKI can decrease or increase up to two periods of the low-speed clock
(TXCLKO). Should the delay exceed this amount, the read and write pointers will point to the same word in the
FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow the FIFO control
logic will initiate an OVERFLOW signal that can be used by an external controller to issue a RESET signal. The
chip under the control of the FIFO_AUTORST pin can automatically recover from an overflow condition. When
the FIFO_AUTORST input is set to a "High" level, once an overflow condition is detected, the chip will set the
OVERFLOW pin to a high level and will automatically reset and center the FIFO. For the transparent mode of
operation (no FIFO), the RESET should be held at a constant "High" state.
3.4
FIFO Calibration Upon Power Up
It is required that the FIFO_RST pin be pulled "High" for 10 TXCLK cycles to flush out the FIFO after the device
is powered on. If the FIFO experiences an Overflow condition, FIFO_RST can be used to manually reset the
FIFO. However, the OC-48 transceiver has an automatic reset pin that will allow the FIFO to automatically
reset upon an Overflow condition. FIFO_AUTORST should be pulled "High" to enable the automatic FIFO
reset function.
Transmit FIFO
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
S
YMBOL
P
ARAMETER
M
IN
.
T
YP
.
M
AX
.
U
NITS
C
ONDITIONS
TX
TS
TxCLKIP/N "High" to data setup time
300
pS
TX
TH
TxCLKIP/N "High" to data hold time
300
pS
TX
DTY
TxCLKIP/N Duty Cycle
40
60
%
TX
TS
TX
TH
TxCLKIP/N
TxDI[3:0]P/N
相關PDF資料 |
PDF描述 |
|---|---|
| XRT91L81IB | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT94L31_07 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XRT91L81IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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