參數(shù)資料
型號： XRT91L81
廠商： Exar Corporation
英文描述： 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： 2.488/2.666GBPS OC-48/STM-16的SONET / SDH收發(fā)器
文件頁數(shù)： 15/40頁
文件大?。?/td> 264K
代理商： XRT91L81
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
REV. P1.0.3
13
2.0
RECEIVE SECTION
The receive section of XRT91L81 includes the differential limiting amplifier inputs RXINP/N, followed by the
clock and data recovery unit (CDR) and receive serial-to-parallel converter. The integrated limiting amplifier,
designed to be AC coupled at the input, allows the reception of differential signals as low as 10 mV-pp. The
receiver accepts the high speed Non-Return to Zero (NRZ) serial data at 2.488/2.666 Gb/s through the
differential limiting amplifier input interfaces RXINP/N. The clock and data recovery unit recovers the high-
speed receive clock from the incoming scrambled NRZ data stream. The recovered serial data is converted
into 4-bit-wide 622.08/666 Mb/s parallel data and presented to the RXD[3:0]P/N LVDS parallel interface. A
divide-by-4 version of the high-speed recovered clock RXCLKP/N, is used to synchronize the transfer of the 4-
bit RXD[3:0]P/N data with the receive portion of the Upstream device. Upon initialization or loss of signal or
loss of lock the 155.52/77.76 MHz (166/83.3 MHz) external reference clock is used to start-up the clock
recovery phase-locked loop for proper operation. A special loop-back feature can be configured when
RLOOPP is used in conjunction with de-jittered loop-time mode that allows the re-transmitted data to comply
with ITU and Bellcore jitter generation specifications.
2.1
Receive Serial Input
The receive serial inputs can be applied to either the primary or secondary inputs selected by RXSEL. If
RXSEL is pulled "Low", the primary channel RXI0P/N is active. If RXSEL is pulled "High", the secondary
channel RXI1P/N is active. The receive serial inputs should be AC coupled to an optical module or an
electrical interface. A simplified block diagram is shown in Figure 3.
N
OTE
:
Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors
are not necessary and can be excluded.
F
IGURE
3. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
OC-48
Transceiver
Optical Module
0.1
μ
F
0.1
μ
F
RXI0P
RXI0N
相關(guān)PDF資料
PDF描述
XRT91L81IB 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT94L31_07 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
XRT94L31 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L82IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*