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參數(shù)資料
| 型號： | XRT91L81 |
| 廠商： | Exar Corporation |
| 英文描述： | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| 中文描述： | 2.488/2.666GBPS OC-48/STM-16的SONET / SDH收發(fā)器 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大小： | 264K |
| 代理商： | XRT91L81 |
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XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
HARDWARE CONTROL
REV. P1.0.3
5
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
RLOOPS
LVTTL
I
C10
Serial Remote Loopback
Hardware Mode
The serial remote loopback mode intercon-
nects the receive serial input data to the transmit serial output
data. If serial remote loopback is enabled, the 4-bit parallel
transmit input data is ignored while the 4-bit parallel receive out-
put data is maintained.
"Low" = Disabled
"High" = Serial Remote Loopback Mode Enabled
RLOOPP
LVTTL
I
A11
Parallel Remote Loopback
Hardware Mode
The parallel remote loopback mode allows the
input serial data stream to pass through the clock and data
recovery circuit and loopback at the parallel interface to the
serial output port. The 4-bit parallel transmit input data is
ignored while the 4-bit parallel receive output data is main-
tained.
"Low" = Disabled
"High" = Parallel Remote Loopback Mode Enabled
DLOOP
LVTTL
I
B6
Digital Loopback
Hardware Mode
The digital loopback mode interconnects the
4-bit parallel transmit input data and TxCLK to the 4-bit parallel
receive output data and RxCLK respectively while maintaining
the transmit serial output data. If digital loopback is enabled,
the receive serial input data is ignored.
"Low" = Disabled
"High" = Digital Loopback Mode Enabled
N
OTE
:
DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature.
LPTIME_JA
LVTTL
I
C6
Loop Timing Mode With JA
The LPTIME_JA pin must be set "High" in order to select the
recovered receive clock as the reference source for the de-jitter
PLL.
"Low" = Disabled
"High" = Enabled
LPTIME_NO_JA
LVTTL
I
P2
Loop Timing Mode With No JA
When the loop timing mode is activated the external reference
clock to the input of the CMU is replaced with the 1/16th or the
1/32nd of the high-speed recovered receive clock from the
CDR.
"Low" = Disabled
"High" = Loop timing Activated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L81IB | 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82IB | 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT94L31_07 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC |
| XRT94L31 | 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L81IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L82IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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