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參數(shù)資料
| 型號(hào)： | ZL38001DGA |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller with Low ERL Compensation |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PDSO36 |
| 封裝： | 0.300 INCH, QSOP-36 |
| 文件頁(yè)數(shù)： | 40/47頁(yè) |
| 文件大?。?/td> | 668K |
| 代理商： | ZL38001DGA |
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ZL38001
Data Sheet
40
Zarlink Semiconductor Inc.
Register Table 19 - Send ERROR Peak Detect Register 2 (SEPD2)
Register Table 20 - Send (Sout) Peak Detect Register 1 (SOPD1)
Bit
Name
Description
7
SEPD
15
SEPD
14
SEPD
13
SEPD
12
SEPD
11
SEPD
10
SEPD
9
SEPD
8
These peak detector registers allow the user to monitor the error signal peak
level in the send path at reference point S2 (see Figure 1). The information is
in 16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
6
5
4
3
2
1
0
Bit
Name
Description
7
SOPD
7
SOPD
6
SOPD
5
SOPD
4
SOPD
3
SOPD
2
SOPD
1
SOPD
0
These peak detector registers allow the user to monitor the Send out signal
(Sout) peak level at reference point S3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
6
5
4
3
2
1
0
External Read Address: 39
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
SEPD
15
SEPD
14
SEPD
13
SEPD
12
SEPD
11
SEPD
10
SEPD
9
SEPD
8
External Read Address: 1A
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
SOPD
7
SOPD
6
SOPD
5
SOPD
4
SOPD
3
SOPD
2
SOPD
1
SOPD
0
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| ZL38001 | Low-Voltage Acoustic Echo Canceller with Low ERL Compensation |
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