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參數(shù)資料
| 型號(hào)： | ZL38001DGA |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller with Low ERL Compensation |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PDSO36 |
| 封裝： | 0.300 INCH, QSOP-36 |
| 文件頁(yè)數(shù)： | 41/47頁(yè) |
| 文件大?。?/td> | 668K |
| 代理商： | ZL38001DGA |
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ZL38001
Data Sheet
41
Zarlink Semiconductor Inc.
Register Table 21 - Send (Sout) Peak Detect Register 2 (SOPD2)
Register Table 22 - Rout Limiter Register 1 (RL1)
Bit
Name
Description
7
SOPD
15
SOPD
14
SOPD
13
SOPD
12
SOPD
11
SOPD
10
SOPD
9
SOPD
8
These peak detector registers allow the user to monitor the Send out signal
(Sout) peak level at reference point S3 (see Figure 1). The information is in
16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
6
5
4
3
2
1
0
Bit
Name
Description
7
L
0
This bit is used in conjunction with Rout Limiter Register 2. (See description
below.)
6
-
RESERVED
5
-
4
-
3
-
2
-
1
-
0
-
External Read Address: 1B
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
SOPD
15
SOPD
14
SOPD
13
SOPD
12
SOPD
11
SOPD
10
SOPD
9
SOPD
8
External Read Address: 24
H
Reset Value: 80
H
7
6
5
4
3
2
1
0
L
0
-
-
-
-
-
-
-
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