參數(shù)資料
型號(hào)： ZL38001QDC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： Low-Voltage Acoustic Echo Canceller with Low ERL Compensation
中文描述： DATACOM, ISDN ECHO CANCELLER, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, MS-026ABC, TQFP-48
文件頁數(shù)： 19/47頁
文件大?。?/td> 668K
代理商： ZL38001QDC
ZL38001
Data Sheet
19
Zarlink Semiconductor Inc.
and CPHA=0). This means that during a write to the ZL38001, by the Motorola processor, output data from the
DATA1 pin must be ignored. This also means that input data on the DATA2 pin is ignored by the ZL38001 during a
valid read by the Motorola processor.
All data transfers through the microport are two bytes long. This requires the transmission of a Command/Address
byte followed by the data byte to be written to or read from the addressed register. CS must remain low for the
duration of this two-byte transfer. As shown in Figures 8 and 9, the falling edge of CS indicates to the ZL38001 that
a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used
to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information
detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock
cycles are used to transfer the data byte between the ZL38001 and the microcontroller. At the end of the two-byte
transfer, CS
is brought high again to terminate the session. The rising edge of CS
will tri-state the DATA1 pin. The
DATA1 pin will remain tri-stated as long as CS
is high.
Intel processors utilize Least Significant Bit (LSB) first transmission while Motorola/National processors use Most
Significant Bit (MSB) first transmission. The ZL38001 microport automatically accommodates these two schemes
for normal data bytes. However, to ensure timely decoding of the R/W and address information, the
Command/Address byte is defined differently for Intel and Motorola/National operations. Refer to the relative timing
diagrams of Figure 8 and Figure 9. Receive data bits are sampled on the rising edge of SCLK while transmit data is
clocked out on the falling edge of SCLK. Detailed microport timing is shown in Figure 14 and Figure 15.
3.1 Bootload Process and Execution from RAM
A bootloadable program RAM (BRAM) is available on the ZL38001 to support factory-issued software upgrades to
the built-in algorithm. To make use of this bootload feature, users must include 4096 X 8 bits of memory in their
microcontroller system (i.e., external to the ZL38001), from which the ZL38001 can be bootloaded. Registers and
program data are loaded into the ZL38001 in the same fashion via the serial microport. Both employ the same
command / address / data byte specification described in the previous section on serial microport. Either intel or
motorola mode may be transparently used for bootloading. There are also two registers relevant to bootloading
(BRC=control and SIG=signature, see Register Summary). The effect of these register values on device operation
is summarized in Table 5.
Bootload mode is entered and exited by writing to the bootload bit in the Bootload RAM Control (BRC) register at
address 3fh (see Register Summary). During bootload mode, any serial microport "write" (R/W command bit =0) to
an address other than that of the BRC register will contribute to filling the program BRAM. Call these transactions
"BRAM-fill" writes. Although a command/address byte must still precede each data byte (as described for the serial
microport), the values of the address fields for these "BRAM-fill" writes are ignored (except for the value 3fh, which
designates the BRC register.) Instead, addresses are internally generated by the ZL38001 for each "BRAM-fill"
write. Address generation for "BRAM-fill" writes resumes where it left off following any read transaction while
bootload mode is enabled. The first 4096 such "BRAM-fill" writes while bootload is enabled will load the memory,
but further ones after that are ignored. Following the write of the first 4096 bytes, the program BRAM will be filled.
Before bootload
mode is disabled
, it is recommended that users then read back the value from the signature
register (SIG) and compare it to the one supplied by the factory along with the code. Equality verifies that the
correct data has been loaded. The signature calculation uses an 8-bit MISR which only incorporates input from
"BRAM-fill" writes. Resetting the bootload bit (
C
2
) in the BRC register to 0 (see Register Summary) exits bootload
mode, resetting the signature (SIG) register and internal address generator for the next bootload. A hardware reset
(RESET=0) similarly returns the ZL38001 to the ready state for the start of a bootload.
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