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參數(shù)資料
| 型號(hào)： | ZL38001QDC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller with Low ERL Compensation |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, MS-026ABC, TQFP-48 |
| 文件頁(yè)數(shù)： | 20/47頁(yè) |
| 文件大?。?/td> | 668K |
| 代理商： | ZL38001QDC |
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ZL38001
Data Sheet
20
Zarlink Semiconductor Inc.
Note: bits C
1
C
0
are reserved, and must be set to zero.
FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM
BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM)
BRC Register
Bits
C
3
C
2
C
1
C
0
X 1 0 0
R/W
Address
Data
W
3fh
(= 1 1 1 1 1 1 b)
Writes "data" to BRC reg.
- Bootload frozen; BRAM contents are NOT affected.
W
other than 3fh
Writes "data" to next byte in BRAM (bootloading.)
R
1 x x x x x b
Reads back "data" = BRC reg value.
- Bootload frozen; BRAM contents are NOT affected.
R
0 x x x x x b
Reads back "data" = SIG reg value.
- Bootload frozen; BRAM contents are NOT affected.
NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs)
BRC Register
Bits
C
3
C
2
C
1
C
0
X 0 0 0
R/W
Address
Data
W
any
(=
a
5
a
4
a
3
a
2
a
1
a
0
b)
Writes "data" to corresponding DREG.
R
any
(=
a
5
a
4
a
3
a
2
a
1
a
0
b)
Reads back "data" = corresponding DREG value.
PROGRAM EXECUTION MODES
C
3
C
2
C
1
C
0
0 0 0 0
Execute program in ROM, bootload mode disabled.
- BRAM address counter reset to initial (ready) state.
- SIG reg reseeded to initial (ready) state
C
3
C
2
C
1
C
0
0 1 0 0
Execute program in ROM, while bootloading the RAM.
- BRAM address counter increments on microport writes (except to 3fh)
- SIG reg recalculates signature on microport writes (except to 3fh)
C
3
C
2
C
1
C
0
1 0 0 0
Execute program in RAM, bootload mode disabled.
- BRAM address counter reset to initial (ready) state.
- SIG reg reseeded to initial (ready) state
C
3
C
2
C
1
C
0
1 1 0 0
- NOT RECOMMENDED -
(Execute program in RAM, while bootloading the RAM)
Table 5 - Bootload RAM Control (BRC) Register States
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