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參數(shù)資料
| 型號： | ZL38001QDC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller with Low ERL Compensation |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, MS-026ABC, TQFP-48 |
| 文件頁數(shù)： | 22/47頁 |
| 文件大?。?/td> | 668K |
| 代理商： | ZL38001QDC |
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ZL38001
Data Sheet
22
Zarlink Semiconductor Inc.
Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire
X
A
0
A
1
A
2
A
3
A
4
A
5
R/W
COMMAND/ADDRESS
DATA INPUT
DATA 2
Receive
DATA 1
Transmit
SCLK
CS
D
D
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38001.
The ZL38001:
outputs transmit data on the falling edge of SCLK
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
High Impedance
DATA OUTPUT
latches receive data on the rising edge of SCLK
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