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參數(shù)資料
| 型號： | ZL38001QDC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Low-Voltage Acoustic Echo Canceller with Low ERL Compensation |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, MS-026ABC, TQFP-48 |
| 文件頁數(shù)： | 35/47頁 |
| 文件大?。?/td> | 668K |
| 代理商： | ZL38001QDC |
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ZL38001
Data Sheet
35
Zarlink Semiconductor Inc.
Register Table 9 - Double Talk detection Threshold Register (DTDT)
Register Table 10 - Receive (Rin) Peak Detect Register 1 (RIPD1)
Bit
Name
Description
7
DTDT
2
DTDT
1
DTDT
0
6
5
4
-
RESERVED. Must keep as 0.
3
-
RESERVED. Must keep as 0.
2
-
RESERVED. Must keep as 0.
1
-
RESERVED. Must keep as 0.
0
-
RESERVED. Must keep as 1.
Bit
Name
Description
7
RIPD
7
RIPD
6
RIPD
5
RIPD
4
RIPD
3
RIPD
2
RIPD
1
RIPD
0
These peak detector registers allow the user to monitor the receive in signal
(Rin) peak level at reference point R1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
6
5
4
3
2
1
0
External Read/Write Address: 31
H
Reset Value: 21
H
7
6
5
4
3
2
1
0
DTDT
2
DTDT
1
DTDT
0
-
-
-
-
-
DTDT
2,
DTDT
1,
DTDT
0
Value
DTDT
DTDT
2,
DTDT
1,
DTDT
0
Value
DTDT
000
-12 dB
100
+12 dB
001
-6 dB
101
+18 dB
010
0 dB
110
+24 dB
011
+6 dB
111
+30 dB
External Read Address: 16
H
Reset Value: 00
H
7
6
5
4
3
2
1
0
RIPD
7
RIPD
6
RIPD
5
RIPD
4
RIPD
3
RIPD
2
RIPD
1
RIPD
0
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