參數(shù)資料
型號： ZL50015QCC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝： 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù)： 43/122頁
文件大?。?/td> 926K
代理商： ZL50015QCC
ZL50015
Data Sheet
43
Zarlink Semiconductor Inc.
13.3 Output Frequencies
The DPLL generates a limited number of output signals. All signals are synchronous to each other and in the
normal operating mode, are locked to the selected input reference. The DPLL provides outputs with the following
frequencies:
13.4 Pull-In/Hold-In Range (also called Locking Range)
The widest tolerance required for any of the given input clock frequencies is
±
130 ppm for the T1 clock
(1.544 MHz). If the system clock (crystal/oscillator) accuracy is
±
30 ppm, it requires a minimum pull-in range of
±
160 ppm. Users who do not require the
±
30 ppm freerun accuracy of the DPLL can use a
±
100 ppm system clock.
Therefore the pull-in range is a minimal
±
230 ppm. The pull-in range of this device is
±
260 ppm.
14.0 Jitter Performance
14.1 Input Clock Cycle to Cycle Timing Variation Tolerance
The ZL50015 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50015
to synchronize off a low cost DPLL when it is in either Divided Slave mode or Multiplied Slave mode.
14.2 Input Jitter Acceptance
The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the
input clock that the DPLL must accept without making cycle slips or losing lock. The lower the jitter frequency, the
larger the jitter acceptance. For jitter frequencies below a tenth of the cut-off frequency of the DPLL's jitter transfer
function, any input jitter will be followed by the DPLL. The maximum value of jitter tolerance for the DPLL is
±
1023UI
p-p
.
14.3 Jitter Transfer Function
The corner frequency (-3 dB) of the Stratum 4E DPLL is 15.2 Hz.
CKo0
CKo1
CKo2
CKo3
CKo4
CKo5
FPo0
FPo1
FPo2
FPo3
FPo5
4.096 MHz
8.192 MHz
16.384 MHz
4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
1.544 MHz or 2.048 MHz
19.44 MHz
8 kHz (244 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (61 ns wide pulse)
8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse)
8 kHz (51 ns wide pulse)
Table 10 - Generated Output Frequencies
相關(guān)PDF資料
PDF描述
ZL50015QCC1 Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL
ZL50018GAC 2 K Digital Switch with Enhanced Stratum 3 DPLL
ZL50018QCC 2 K Digital Switch with Enhanced Stratum 3 DPLL
ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZL50015QCC1 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015QCG1 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:PB FREE 1K+RATE CONVERSION AND S4E DPLL 制造商:Microsemi Corporation 功能描述:PB FREE 1K+RATE CONVERSION AND S4E DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 1K-CH ENH 256LQFP 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 1K-CH ENH 256LQFP
ZL50016 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch
ZL50016_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch
ZL50016GAC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 1K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 1K-CH ENH 256PBGA
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