參數(shù)資料
型號: ZL50015QCC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù): 92/122頁
文件大?。?/td> 926K
代理商: ZL50015QCC
ZL50015
Data Sheet
92
Zarlink Semiconductor Inc.
26.0 DC Parameters
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (
V
IN
).
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
1
2
3
4
5
6
7
I/O Supply Voltage
Core Supply Voltage
Input Voltage
Input Voltage (5 V-tolerant inputs)
Continuous Current at Digital Outputs
Package Power Dissipation
Storage Temperature
V
DD_IO
V
DD_CORE
V
I_3V
V
I_5V
I
o
P
D
T
S
-0.5
-0.5
-0.5
-0.5
5.0
2.5
V
V
V
V
V
DD
+ 0.5
7.0
15
1.5
+125
mA
W
°
C
- 55
Recommended Operating Conditions -
Voltages are with respect to ground (V
SS
) unless otherwise stated
.
Characteristics
Sym.
Min.
Typ.
Max.
Units
1
2
3
4
5
Operating Temperature
Positive Supply
Positive Supply
Input Voltage
Input Voltage on 5 V-Tolerant Inputs
T
OP
V
DD_IO
V
DD_CORE
V
I
V
I_5V
-40
3.0
1.71
0
0
25
3.3
1.8
3.3
5.0
+85
3.6
1.89
V
DD_IO
5.5
°
C
V
V
V
V
DC Electrical Characteristics
-
Voltages are with respect to ground (V
ss
) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
5
Supply Current - V
DD_CORE
Supply Current - V
DD_IO
Input High Voltage
Input Low Voltage
Input Leakage (input pins)
Input Leakage (bi-directional pins)
Weak Pullup Current
Weak Pulldown Current
Input Pin Capacitance
Output High Voltage
10 Output Low Voltage
11 Output High Impedance Leakage
12 Output Pin Capacitance
I
DD_CORE
I
DD_IO
V
IH
V
IL
I
IL
I
BL
I
PU
I
PD
C
I
V
OH
V
OL
I
OZ
C
O
150
45
mA
mA
V
V
μ
A
μ
A
μ
A
μ
A
pF
V
V
μ
A
pF
C
L
= 30 pF
2.0
0.8
5
5
0
<V
IN
V
DD_IO
See Note 1
Input at 0 V
Input at V
DD_IO
6
7
8
9
-33
33
3
2.4
I
OH
= 10 mA
I
OL
= 10 mA
0 < V < V
DD
0.4
5
10
5
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