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參數(shù)資料
| 型號： | ZL50015QCC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP256 |
| 封裝： | 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256 |
| 文件頁數(shù)： | 49/122頁 |
| 文件大小： | 926K |
| 代理商： | ZL50015QCC |
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ZL50015
Data Sheet
49
Zarlink Semiconductor Inc.
20.0 Quadrant Frame Programming
By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 15), users can divide one frame of input
data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or
zero for robbed-bit signaling. The four quadrant frames are defined as follows:
When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit
5 - 3) or STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or MSB of every input channel in the quadrant is forced to “1”
or “0” as shown by the following table:
Note that Quadrant Frame Programming and BER reception cannot be used simultaneously on the same input
stream.
21.0 JTAG Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The
operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
21.1 Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50015 test functions. It consists of three input pins and one output pin
as follows:
Test Clock Input (TCK)
- TCK provides the clock for the test logic. TCK does not interfere with any on-chip
clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of
the Boundary-Scan register cells concurrently with the operation of the device and without interfering with
the on-chip logic.
Test Mode Selection Inputs (TMS)
- The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to high when it is not driven from an external source.
Data Rate
Quadrant 0
Quadrant 1
Quadrant 2
Quadrant 3
2.048 Mbps
Channel 0 - 7
Channel 8 - 15
Channel 16 - 23
Channel 24 - 31
4.096 Mbps
Channel 0 - 15
Channel 16 - 31
Channel 32 - 47
Channel 48 - 63
8.192 Mbps
Channel 0 - 31
Channel 32 - 63
Channel 64 - 95
Channel 96 - 127
16.384 Mbps
Channel 0 - 63
Channel 64 - 127
Channel 128 - 191
Channel 192 - 255
Table 14 - Definition of the Four Quadrant Frames
STIN[n]Q[y]C[2:0]
Action
0xx
100
101
110
111
Normal Operation
Replaces LSB of every channel in Quadrant y with ‘0’
Replaces LSB of every channel in Quadrant y with ‘1’
Replaces MSB of every channel in Quadrant y with ‘0’
Replaces MSB of every channel in Quadrant y with ‘1’
Note:
y = 0, 1, 2, 3
Table 15 - Quadrant Frame Bit Replacement
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| ZL50018QCC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50015QCC1 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch with Stratum 4E DPLL |
| ZL50015QCG1 | 制造商:Microsemi Corporation 功能描述: 制造商:Microsemi Corporation 功能描述:PB FREE 1K+RATE CONVERSION AND S4E DPLL 制造商:Microsemi Corporation 功能描述:PB FREE 1K+RATE CONVERSION AND S4E DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 1K-CH ENH 256LQFP 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 1K-CH ENH 256LQFP |
| ZL50016 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch |
| ZL50016_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 1 K Digital Switch |
| ZL50016GAC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 1K X 1K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 1K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 1K-CH ENH 256PBGA |
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