參數(shù)資料
型號: ZL50015QCC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù): 96/122頁
文件大?。?/td> 926K
代理商: ZL50015QCC
ZL50015
Data Sheet
96
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Figure 28 - Intel Non-Multiplexed Bus Timing - Read Access
AC Electrical Characteristics
- Intel Non-Multiplexed Bus Mode - Read Access
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
2
1
2
3
4
5
6
7
8
9
CS de-asserted time
RD setup to CS falling
WR setup to CS falling
Address setup to CS falling
RD hold after CS rising
WR hold after CS rising
Address hold after CS rising
Data setup to RDY high
Data hold after CS rising
t
CSD
t
RS
t
WS
t
AS
t
RH
t
WH
t
AH
t
DS
t
DH
15
10
10
5
0
0
0
8
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 50 pF
C
L
= 50 pF, R
L
= 1 K
(Note 1)
10 Acknowledgement delay time.
From CS low to RDY high:
Registers
Memory
t
AKD
75
185
12
ns
ns
ns
C
L
= 50 pF
C
L
= 50 pF
11 Acknowledgement hold time.
From CS high to RDY low
12 RDY drive low to HiZ
t
AKH
4
C
L
= 50 pF, R
L
= 1 K
(Note 1)
t
AKZ
8
ns
Note 1:
High impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to
discharge C
L
.
A delay of 500
μ
s to 2 ms (see Section 17.2 on page 46) must be applied before the first microprocessor access is
performed after the RESET pin is set high.
Note 2:
CS
A0-A13
D0-D15
t
AH
t
WS
WR
t
WH
t
AKD
t
DS
t
AKH
RDY
V
CT
V
CT
V
CT
V
CT
V
CT
VALID ADDRESS
VALID READ DATA
t
CSD
t
AKZ
t
RS
RD
t
RH
V
CT
t
AS
t
DH
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