參數(shù)資料
型號: ZL50015QCC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Enhanced 1 K Digital Switch with Stratum 4E DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PQFP256
封裝: 28 X 28 MM, 1.40 MM HEIGHT, MS-026BJC, LQFP-256
文件頁數(shù): 70/122頁
文件大?。?/td> 926K
代理商: ZL50015QCC
ZL50015
Data Sheet
70
Zarlink Semiconductor Inc.
6 - 5
PRS1 - 0
Preferred Reference Selection Bits
These bits select the preferred reference from one of the input references. They are used
only if the PMS2-0 bits are set to 001. Otherwise, these bits are ignored
4 - 2
PMS2 - 0
Preference Mode Selection Bits
These bits select one of the preference modes:
If in automatic mode with a preferred reference (PMS2-0 = 001 and FDM1-0 = 00), the
automatic state machine will only switch between two references (as per Table 8). Please
see Section 12.1.3.2, “Automatic Reference Switching With Preferences“ on page 40 for
more details.
1 - 0
FDM1 - 0
Force DPLL Timing Mode
These bits force the DPLL into one of the valid operation modes.
Bit
Name
Description
Table 34 - Reference Change Control Register (RCCR) Bits (continued)
External Read/Write Address: 004B
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
MTR
PRS
1
PRS
0
PMS
2
PMS
1
PMS
0
FDM
1
FDM
0
PRS1
PRS0
Preferred Reference Selection
0
0
REF0
0
1
REF1
1
0
REF2
1
1
REF3
PMS2
PMS1
PMS0
Preference Mode
0
0
0
No Preference
0
0
1
Preference as per the setting
of the PRS1 - 0 bits
0
1
0
Force REF0
0
1
1
Force REF1
1
0
0
Force REF2
1
0
1
Force REF3
110 - 111
Reserved
FDM1
FDM0
DPLL TIMING Mode
0
0
Automatic
0
1
Normal
1
0
Holdover
1
1
Freerun
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
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