305
CHAPTER 13 A/D CONVERTER
13.2 A/D Converter Mode Register (ADM)
ADM is an 8-bit register that controls A/D converter operations.
The ADM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Its format
is shown in Figure 13-3.
Bits 0 through 2 (ANIS0 through ANIS2) select input analog signals to be converted. Bit 3 (PS) selects whether ANI0
through ANI7 (low-order 8 channels) or ANI8 through ANI15 (high-order 8 channels) are used as analog input pins. The
low-order 8 channels and high-order 8 channels have identical functions.
Bit 5 (AM0) and bit 6 (AM1) control the operation mode of A/D conversion. If the AM0 and AM1 bits are cleared (0), all
conversion operations under execution are stopped. At this time, ADCRn (n = 0 to 7) is not updated, nor is the INTAD interrupt
request generated. Moreover, power supply to the voltage comparator is stopped to reduce the current consumption of
the A/D converter.
Bit 7 (TRG) enables external synchronization of the A/D conversion operation. If the TRG bit is set (1) when the AM0
or AM1 bits are set, the conversion operation is initialized each time the valid edge is input to the INTP4 pin as an external
trigger. If the TRG bit is cleared (0), the conversion operation is performed regardless of the INTP4 pin input.
If data is written to ADM during conversion, the conversion operation is initialized and started from the beginning again.
When RESET is input, the value of ADM is reset to 00H.
Caution When the STOP mode or IDLE mode is used, the consumption current should be reduced by clearing
(0) the AM0 bit and AM1 bit before entering the STOP or IDLE mode. If the AM0 bit or AM1 bit remains
set (1), the conversion operation will be stopped by entering the STOP or IDLE mode, but the power
supply to the voltage comparator will not be stopped, and therefore the A/D converter consumption
current will not be reduced.