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CHAPTER 4 CLOCK GENERATOR
4.3 Clock Generator Operation
4.3.1 Clock oscillator
(1) When using crystal/ceramic oscillation
The clock oscillator starts oscillating when the RESET signal is input, and stops oscillation when the STOP mode is set
by the standby control register (STBC). Oscillation is resumed when the STOP mode is released.
(2) When using external clock
The clock oscillator supplies the clock input from the X1 pin to the internal circuitry when the RESET signal is input.
The oscillator operates as follows when the EXTC bit of the oscillation stabilization time specification register (OSTS)
is set to 1.
The clock oscillator supplies the clock input to the X2 pin to the internal circuitry.
The necessary circuit stops operating during the crystal/ceramic oscillation of the clock oscillator, to reduce the power
dissipation.
The STOP mode can be used even when the external clock is input.
Cautions 1. When using a crystal/ceramic oscillation, the EXTC bit of the Oscillation stabilization time specifica-
tion register (OSTS) must be cleared (0). If the EXTC bit is set (1), oscillation will stop.
2. If the STOP mode is used with external clock input, the EXTC bit of the OSTS must be set (1) before
setting the STOP mode. If the STOP mode is used when the EXTC bit is in the cleared (0) state, not
only will the clock generator consumption current not be reduced, but the
m
PD784046 may also be
damaged or suffer reduced reliability.
3. When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock
input to the X1 pin, to the X2 pin.
4.3.2 Frequency divider
The frequency divider divides the output from the clock oscillator by two, and supplies the result to the CPU and peripheral
hardware.