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CHAPTER 4 INTERFACES
112
Input the clock recovery training clock to the REFCLK pin.
Pin
Use
Connection value
REFCLK
Inputs the reference clock for clock recovery training.
19.44 MHz
Receive clock recovery PLL function
The clock recovery PLL extracts the receive clock from the receive data strings input to the RDIT/RDIC pin.
The
μ
PD98405 contains an OOL (Out of Link) detection circuit. This circuit monitors whether the receive
clock recovery PLL has successfully been locked to the receive data string to extract an expected clock.
The circuit compares an eight-divided clock, generated by the PLL, with the clock frequency input to the
REFCLK pin. When the difference is more than 243 ppm, the circuit assumes that the receive clock
recovery PLL has failed to lock successfully and enters the OOL status. When the difference is less than
244 ppm, the OOL status is released. The OOL status is applied to a bit of the PICR register and can
cause an interrupt.
Transmit PLL function
A transmit clock in a range of between 19.44 and 155.52 MHz can be generated using the internal
synthesizer.
Figure 4-39. Synthesizer Reference Clock
Clock
recovery
RDIT, RDIC
(Rx side data)
REFCLK
(19.44 MHz)
155.52 MHz
→
19.44 MHz
Serial/Parallel
converter
recovery clock
(155.52 MHz)
recovery data
(155.52 MHz)
RCL (19.44 MHz)
(Rx side system clock)
Rx Parallel Data[7:0]
(recovery data)
19.44 MHz
→
155.52 MHz
Parallel/Serial
converter
TCL (19.44 MHz)
(Tx side system clock)
Tx Parallel Data[7:0]
(Tx side data)
TDOT, TDOC
(Tx side data)
synthesized clock
(155.52 MHz)
Clock
synthesizer