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CHAPTER 7 REGISTERS
326
(5) Mode register 2 (MDR2)
This register is used to select the mode of the
μ
PD98405.
Register name
D7
D6
D5
D4
D3
D2
D1
D0
Address
Default
R/W
MDR2
0
oolenb idlenb
LP1
LP0
RxCL RCM1 RCM0
04H
00H
R/W
Field
Function
Default value
Used to set the automatic switching function of the receive clock in the OOL
status.
1
Uses the receive clock when the receive clock recovery PLL has failed to
lock successfully (OOL status).
0
Automatically uses the transmission clock as the receive clock in the
OOL status.
Used to select the format of a free cell to insert.
1
Inserts an unassigned cell as a free cell.
D6: oolenb
0
D5: idlenb
0
Inserts an idle cell as a free cell.
0
Used to set the loopback mode.
LP[1:0]
00
01
Mode
Sets normal mode.
RPLP mode
Sets loopback from the PMD input to the PMD output,
before the serial/parallel converter circuit.
TPLP mode
Sets loopback from the ATM input to the ATM output,
via the serial/parallel converter circuit.
Cannot be set.
10
11
D4: LP1
D3: LP0
00
Used to select the source of the receive clock.
1
Uses the clock generated by the transmission synthesizer PLL as the
receive clock.
0
Uses the clock extracted by the receive clock recovery PLL as the
receive clock.
Used to select the interrupt mode.
D2: RxCL
0
RCM[1:0]
00
Mode
Selects interrupt mode 1.
The bits of the PHY interrupt registers are held as is
until read by the host. Even if the source target is
cleared, the status bit remains set.
Selects interrupt mode 2.
Even if the host reads the contents of a PHY interrupt
register, the bits are not reset. The status remains set
until the source itself is cleared.
Selects interrupt mode 3.
Even if the cause of an interrupt has not been cleared,
this bit is reset when the host reads the PHY interrupt
register.
PHY interrupt registers: PICR, ACR, PCR
For details of operations of these registers, see
Section 6.8
.
01
1X
D1: RCM1
D0: RCM0
00
Remark
Upon reading this register, 0 is returned for the D7 bit. It is not possible to write to the D7 bit.