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CHAPTER 8 JTAG BOUNDARY SCAN
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8.6 TAP CONTROLLER INITIALIZATION
TAP controller initialization is explained below.
(1) The TAP controller is not reset upon the occurrence of system input operation such as a system reset.
(2) If the level of the signal being input to the JMS pin is held high while at least five rising edges of the
signal being input to the JCK pin are encountered, the TAP controller enters the Test-Logic-Reset
state.
(3) Upon the occurrence of a JRST_B input, the TAP controller asynchronously enters the Test-Logic-
Reset state.
8.7 INSTRUCTION REGISTER
The use of this register is as defined below (see
Section 8.2
).
(1) To enable their conversion, the instructions that are shift-input into the instruction register are latched
only while the TAP controller is in the Update-IR state or Test-Logic-Reset state.
(2) Between the serial input and serial output of the instruction register, data inversion is not performed.
(3) While the TAP controller is in the Capture-IR state, fixed binary "01" pattern data (where the LSB
(Least Significant Bit) is 1) is loaded into this register cell.
(4) While the TAP controller is in the Test-Logic-Reset state, fixed binary "01" pattern data (where the
LSB (Least Significant Bit) is 1) is set in this register.
(5) While the value in this register is being read, the data is output from the JDO pin, in order from the
LSB to the MSB, every time a falling edge of the signal being input to the JCK pin is detected.
According to the data set in the instruction register, the JTAG boundary scan circuit of the
μ
PD98405 can
support only one of the two instructions listed below.
BYPASS instruction
EXTEST instruction
Instruction register
D1
D0
Supported instruction
0
0
EXTEST instruction
0
1
Not used
1
0
Not used (BYPASS instruction)
1
1
BYPASS instruction