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CHAPTER 7 REGISTERS
305
(16) MBA0 to MBA3 (mailbox bottom address)
Address:
18H - MBA0:
mailbox 0
19H - MBA1:
mailbox 1
1AH - MBA2: mailbox 2
1BH - MBA3: mailbox 3
Access mode: Read/write
MBA0 to MBA3 set the low-order 16 bits of the 32-bit bottom addresses of the four mailboxes set to
system memory. The bottom address stores the address next to the last word in the area used as a
mailbox area. The host sets MBA of the mailbox to be selected from the four mailboxes. For the
μ
PD98405, MSH is used as the high-order 16 bits of an address. The values set to these registers must
not be the same as those set to MSL. The default value after a reset is undefined. It is not possible to
write to bits 31 to 16. Upon a read, 0 is returned.
31
0
MBA0
31
0
MBA1
31
0
MBA2
31
0
MBA3
- 0 -
- 0 -
- 0 -
- 0 -
16
15
16
15
16
15
16
15
(17) MTA0 to MTA3 (mailbox tail address)
Address:
1CH - MTA0: mailbox 0
1DH - MTA1: mailbox 1
1EH - MTA2: mailbox 2
1FH - MTA3:
mailbox 3
Access mode: Read/write
MTA0 to MTA3 store the low-order 16 bits of the read pointers read by the host from the four mailboxes.
These registers are managed by the host. The host writes and updates the start address of the indication
next to that processed each time it has completed processing of the transmit/receive indication. At
initialization, set the same values as those set for MSL. The default value after a reset is undefined. It is
not possible to write to bits 31 to 16. Upon a read, 0 is returned.