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CHAPTER 7 REGISTERS
309
7.3 INDIRECT ADDRESS REGISTER
(1) TOS (top of stack)
Address:
100H
Access mode: Read/write
The host sets the start address of the free block pool of control memory. Subsequently, this register is
managed by the
μ
PD98405 and functions as a pointer to the free block that can be allocated as the VC
table. The default value after a reset is 0. It is not possible to write to bits 31 to 19 or bits 3 to 0. Upon a
read, 0 is returned.
31
0
TOP OF STACK ADDRESS
0
0
18
19
3
4
(2) SCR (shaper control register)
Address:
101H
Access mode: Read/write
The host uses the SCR register to set the number of the shaper that uses the UBR service. Subsequently,
when this shaper is used as the UBR service, the UEN bit is set to 1 (enable). For the shaper set in the
SCR register, set the lowest priority. After a reset, this counter is initialized to 0. It is not possible to write
to bits 31 to 5. Upon a read, 0 is returned.
31
0
SHAPER NO. OF UBR
0
3
4
UEN
5
(3) SPE0 to SPE15 (shaper pointer entry 0 to 15)
Address:
102H - 111H
Access mode: Read/write
The μPD98405 mainly uses the SPE register as a table and manages it. The host accesses this area only
when initializing its value to 0, or when using the cell generator function. Otherwise, the host has no
reason to access this register. SPE0 corresponds to address 102H and shaper number 0, while SPE15
corresponds to address 111H and shaper number 15. The default value will be 0 after a reset. It is not
possible to write to bits 29 to 15. Upon a read, 0 is returned.
30
31
0
0
14
15
VC Number
u
a
29