20695H/0—March 1998
AMD-K6
Processor Data Sheet
Preliminary Information
Chapter 1
AMD-K6
Processor
5
1
AMD-K6
Processor
I
Advanced 6-Issue RISC86
Superscalar Microarchitecture
Seven parallel specialized execution units
Multiple sophisticated x86-to-RISC86 instruction decoders
Advanced two-level branch prediction
Speculative execution
Out-of-order execution
Register renaming and data forwarding
Issues up to six RISC86 instructions per clock
Large On-Chip Split 64-Kbyte Level-One (L1) Cache
32-Kbyte instruction cache with additional predecode cache
32-Kbyte writeback dual-ported data cache
MESI protocol support
High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit
High-Performance Industry-Standard MMX Instructions
321-Pin Ceramic Pin Grid Array (CPGA) Package (Socket 7 Compatible)
Industry-Standard System Management Mode (SMM)
IEEE 1149.1 Boundary Scan
Full x86 Binary Software Compatibility
N
N
N
N
N
N
N
I
N
N
N
I
I
I
I
I
I
As the next generation in the AMD K86 family of x86 processors, the innovative
AMD-K6 processor brings industry-leading performance to PC systems running the
extensive installed base of x86 software. In addition, its socket 7 compatible, 321-pin
Ceramic Pin Grid Array (CPGA) package enables the AMD-K6 to reduce
time-to-market by leveraging today’s cost-effective infrastructure to deliver a
superior price/performance PC solution.
To provide state-of-the-art performance, the AMD-K6 processor incorporates the
innovative and efficient RISC86 microarchitecture, a large 64-Kbyte level-one cache
(32-Kbyte dual-ported data cache, 32-Kbyte instruction cache with predecode data), a
powerful IEEE 754-compatible and 854-compatible floating-point execution unit, and
a high-performance multimedia execution unit for executing industry-standard MMX
instructions. These features have been combined to deliver industry leadership in
16-bit and 32-bit performance, providing exceptional performance for both Windows
95 and Windows NT software bases.