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參數(shù)資料
| 型號(hào)： | 256MBDDRSDRAM |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.3 |
| 中文描述： | DDR SDRAM的規(guī)格版本0.3 |
| 文件頁(yè)數(shù)： | 28/51頁(yè) |
| 文件大?。?/td> | 658K |
| 代理商： | 256MBDDRSDRAM |
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Command
< Burst Length=4, CAS Latency= 2, 2.5>
BANK A
ACTIVE
NOP
READ A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
CAS Latency=2
Dout 0 Dout 1 Dout 2 Dout 3
t
RP
* completion of
precharge
Begin Auto-Precharge
DQS
DQ
′
s
CAS Latency=2.5
Dout 0 Dout 1 Dout 2 Dout 3
When the Read with Auto precharge command is issued, new command can be asserted at 3,4 and 5
respectively as follows,
Asserted
command
For same Bank
4
READ+
No AP
For Different Bank
4
3
5
3
5
READ
READ +
No AP
*1
Illegal
Legal
Legal
Legal
READ+AP
READ +
AP
READ +
AP
Illegal
Legal
Legal
Legal
Active
Precharge
*1
: AP = Auto Precharge
Illegal
Legal
Illegal
Legal
Illegal
Illegal
Legal
Legal
Legal
Legal
Legal
Legal
2
0
1
5
3
4
8
6
7
t
RAS(min.)
CK
CK
3.3.11 Read With Auto Precharge
If a read with auto-precharge command is initiated, the DDR SDRAM automatically enters the precharge
operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the
start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation
has started the bank cannot be reactivated and the new command can not be asserted until the precharge
time(tRP) has been satisfied.
Figure 19. Read with auto precharge timing
Table 6. Operating description when new command asserted
while read with auto precharge is issued
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