參數(shù)資料
型號: 256MBDDRSDRAM
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR SDRAM Specification Version 0.3
中文描述: DDR SDRAM的規(guī)格版本0.3
文件頁數(shù): 44/51頁
文件大?。?/td> 658K
代理商: 256MBDDRSDRAM
- 44 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
9. AC Operating Test Conditions
(V
DD
=2.5/3.3V, V
DDQ
=2.5V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * V
DDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V/ns
Input Levels(V
IH
/V
IL
)
V
REF
+0.31/V
REF
-0.31
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
tt
V
Output load condition
See Load Circuit
10. Input/Output Capacitance
(V
DD
=2.5, V
DDQ
=2.5V, T
A
= 25
°
C
,
f=1MHz)
Parameter
Symbol
Min
Max
Delta Cap(max)
Unit
Input capacitance
(A
0
~ A
11
, BA
0
~ BA
1,
CKE, CS, RAS,CAS, WE)
Input capacitance(
CK, CK )
C
IN1
2
3.0
0.5
pF
C
IN2
2
3.0
0.25
pF
Data & DQS input/output capacitance
C
OUT
4.0
5.0
0.5
pF
Input capacitance(DM)
C
IN3
4.0
5.0
pF
Table 16. AC operating test conditions
Table 17. Input/output capacitance
Figure 24. Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
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