參數(shù)資料
型號(hào)： 256MBDDRSDRAM
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR SDRAM Specification Version 0.3
中文描述： DDR SDRAM的規(guī)格版本0.3
文件頁(yè)數(shù)： 6/51頁(yè)
文件大?。?/td> 658K
代理商： 256MBDDRSDRAM
- 6 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
Figure 1 : 256Mb Package Pinout
Figure 2 : Package dimension
Figure 3 :State digram 12
Figure 4 : Power up and initialization sequence
Figure 5 : Mode register set 14
Figure 6 : Mode register set sequence
Figure 7 : Extend mode register set 16
Figure 8 : Bank activation command cycle timing
Figure 9 : Burst read operation timing 19
Figure 10 : Burst write operation timing
Figure 11 : Read interrupted by a read timing 21
Figure 12 : Read interrupted by a write and burst stop timing
Figure 13 : Read interrupted by a precharge timing 22
Figure 14 : Write interrupted by a write timing
Figure 15 : Write interrupted by a read and DM timing 24
Figure 16 : Write interrupted by a precharge and DM timing
Figure 17 : Burst stop timing 26
Figure 18 : DM masking timing
Figure 19 : Read with auto precharge timing 28
Figure 20 : Write with auto precharge timing
Figure 21 : Auto refresh timing 30
Figure 22 : Self refresh timing
Figure 23 : Power down entry and exit timing 31
Figure 24 : Output Load Circuit (SSTL_2)
Figure 25 : I / V characteristics for input/output buffers:
pull-up(above) and pull-down(below) for normal strength driver
Figure 26 : I / V characteristics for input/output buffers:
pull-up(above) and pull-down(below) for half strength driver
Figure 27 : QFC timing on read operation 49
Figure 28 : QFC timing on write operation with tDQSSmax
Figure 29 : QFC timing on write operation with tDQSSmin
Figure 30 : QFC timing example for interrupted writes operation
List of figures
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