參數(shù)資料
型號: 256MBDDRSDRAM
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR SDRAM Specification Version 0.3
中文描述: DDR SDRAM的規(guī)格版本0.3
文件頁數(shù): 50/51頁
文件大?。?/td> 658K
代理商: 256MBDDRSDRAM
- 50 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
QFC timing on Write operation
QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon
as possible after the last DQS-in low going edge.
2
0
1
5
3
4
6
7
Hi-Z
DQS@tDQSSmax
QFC
t
QCSW
*1
t
QCHW min.
Dout 0Dout 1
BL = 2
Write
DQ’S@tDQSSmax
Command
CK
CK
DQS@tDQSSmin
DQ’S@tDQSSmin
2
0
1
5
3
4
6
7
Hi-Z
QFC
t
QCSW
*1
t
QCHW min.
Dout 0 Dout 1
BL = 2
Write
Command
CK
CK
Figure 28. : QFC timing on write operation with tDQSSmax
Figure 29. : QFC timing on write operation with tDQSSmin
*2
t
QCHW max.
*2
t
QCHW max.
1. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC tri-state.
2. The value of tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC tri-state.
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