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參數(shù)資料
| 型號： | 28F640J5 |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲器) |
| 中文描述： | 5伏特英特爾StrataFlash存儲器（5V的6400位英特爾的StrataFlash閃速存儲器） |
| 文件頁數(shù)： | 18/53頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 28F640J5 |
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28F320J5/28F640J5
E
18
PRELIMINARY
4.1
Read Array Command
Upon initial device power-up and after exit from
reset/power-down mode, the device defaults to read
array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, program, or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend
command. The Read Array command functions
independently of the V
PEN
voltage and RP# can be
V
IH
or V
HH
.
4.2
Read Query Mode Command
This section defines the data structure or
“database” returned by the Common Flash Interface
(CFI) Query command. System software should
parse this structure to gain critical information such
as block size, density, x8/x16, and electrical
specifications. Once this information has been
obtained, the software will know which command
sets to use to enable flash writes, block erases, and
otherwise control the flash component. The Query
is part of an overall specification for multiple
command set and control interface descriptions
called Common Flash Interface, or CFI.
4.2.1
QUERY STRUCTURE OUTPUT
The Query “database” allows system software to
gain information for controlling the flash component.
This section describes the device’s CFI-compliant
interface that allows the host system to access
Query data.
Query data are always presented on the lowest-
order data outputs (DQ
0
–7
) only. The numerical
offset value is the address relative to the maximum
bus width supported by the device. On this family of
devices, the Query table device starting address is
a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two bytes of
the Query structure,
“Q” and “R” in ASCII, appear
on the low byte at word addresses 10h and 11h.
This CFI-compliant device outputs 00H data on
upper bytes. Thus, the device outputs ASCII “Q” in
the low byte (DQ
0
–7
) and 00h in the high byte
(DQ
8–15
).
At Query addresses containing two or more bytes
of information, the least significant data byte is
presented at the lower address, and the most
significant data byte is presented at the higher
address.
In all of the following tables, addresses and data
are represented in hexadecimal notation, so the
“h”
suffix has been dropped. In addition, since the
upper byte of word-wide devices is always “00h,”
the leading “00” has been dropped from the table
notation and only the lower byte value is shown.
Any x16 device outputs can be assumed to have
00h on the upper byte in this mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F400B3 | SMART 3 ADVANCED BOOT BLOCK WORD-WIDE |
| 28F400BL-TB | 4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BV-TB | 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 28F400BX-TB | 4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY |
| 28F410-100M1 | 4M-BIT (512K X 8) CMOS FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| 28F640L30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
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