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參數(shù)資料
| 型號(hào)： | 28F640J5 |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲(chǔ)器) |
| 中文描述： | 5伏特英特爾StrataFlash存儲(chǔ)器（5V的6400位英特爾的StrataFlash閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 39/53頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 28F640J5 |
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E
28F320J5/28F640J5
39
PRELIMINARY
Start
Write 60H
Write D0H
Read Status Register
SR.7 =
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Write
Write
Standby
Write FFH after the clear lock-bits operation to place device in read
array mode.
Bus
Operation
Standby
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If an error is detected, clear the status register before attempting retry
or other error recovery.
1
0
Standby
Command
Clear Block
Lock-Bits Setup
Clear Block or
Lock-Bits Confirm
Comments
Data = 60H
Addr = X
Data = D0H
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command
Comments
Check SR.3
1 = Programming Voltage Error
Detect
Check SR.1
1 = Device Protect RP# = V
IH
,
Master Lock-Bit Is Set
Read Status Register
Data (See Above)
Voltage Range Error
Device Protect Error
SR.3 =
SR. 1 =
1
0
1
0
Command Sequence
Error
SR.4,5 =
1
0
Clear Block Lock-Bits
Error
SR.5 =
1
0
Read
Status Register Data
Standby
Check SR.4, 5
Both 1 = Command Sequence
Error
Standby
Check SR.5
1 = Clear Block Lock-Bits Error
Clear Block Lock-Bits
Successful
0606_12
Figure 12. Clear Block Lock-Bit Flowchart
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
| 28F640L30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-Volt I/O (L30) |
| 28F640P3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 28F650 | 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip |
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