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參數(shù)資料
| 型號： | 28F640J5 |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲器) |
| 中文描述： | 5伏特英特爾StrataFlash存儲器（5V的6400位英特爾的StrataFlash閃速存儲器） |
| 文件頁數(shù)： | 26/53頁 |
| 文件大小： | 272K |
| 代理商： | 28F640J5 |
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28F320J5/28F640J5
E
26
PRELIMINARY
4.3
Read Identifier Codes
Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Figure 6 retrieve the manufacturer, device, block
lock configuration and master lock configuration
codes (see Table 13 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read
Identifier
Codes
independently of the V
PEN
voltage and RP# can be
V
IH
or V
HH
. This command is valid only when the
WSM is off or the device is suspended. Following
the Read Identifier Codes command, the following
information can be read:
command
functions
Table 13. Identifier Codes
(1)
Code
Address
(1)
00000
00001
00001
X
0002
(2)
Data
(00) 89
(00) 14
(00) 15
Manufacture Code
Device Code
32-Mbit
64-Mbit
Block Lock Configuration
Block Is Unlocked
Block Is Locked
Reserved for Future Use
Master Lock Configuration
Device Is Unlocked
Device Is Locked
Reserved for Future Use
NOTE:
1.
A
is not used in either x8 or x16 modes when obtaining
the identifier codes. The lowest order address line is A
1
.
Data is always presented on the low byte in x16 mode
(upper byte contains 00h).
2.
X selects the specific block’s lock configuration code.
See Figure 6 for the device identifier code memory
map.
DQ
0
= 0
DQ
0
= 1
DQ
1
–7
00003
DQ
0
= 0
DQ
0
= 1
DQ
1–7
4.4
Read Status Register
Command
The status register may be read to determine when
a block erase, program, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
the first edge of CE
0
, CE
1
, or CE
2
that enables the
device (see Table 2, Chip Enable Truth Table). OE#
must toggle to V
IH
or the device must be disabled
(see Table 2, Chip Enable Truth Table) before
further reads to update the status register latch.
The Read Status Register command functions
independently of the V
PEN
voltage. RP# can be V
IH
or V
HH
.
During a program, block erase, set lock-bit, or clear
lock-bit command sequence, only SR.7 is valid until
the WSM completes or suspends the operation.
Device I/O pins DQ
0
–DQ
6
and DQ
8
–DQ
15
are
placed in a high-impedance state. When the
operation completes or suspends (check status
register bit 7), all contents of the status register are
valid when read.
4.5
Clear Status Register
Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 16).
By allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V
PEN
voltage. RP# can
be V
IH
or V
HH
. The Clear Status Register command
is only valid when the WSM is off or the device is
suspended.
4.6
Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by an block erase confirm.
This command sequence requires an appropriate
address within the block to be erased (erase
changes
all
block
data
preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register
data when read (see Figure 9). The CPU can detect
block erase completion by analyzing the output of
to
FFH).
Block
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相關(guān)代理商/技術(shù)參數(shù) |
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| 28F640L18 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory |
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| 28F640W30 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
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