參數(shù)資料
型號: 28F640J5
廠商: Intel Corp.
英文描述: 5 V Intel StrataFlash Memory(5V 64M位英特爾StrataFlash閃速存儲器)
中文描述: 5伏特英特爾StrataFlash存儲器(5V的6400位英特爾的StrataFlash閃速存儲器)
文件頁數(shù): 8/53頁
文件大?。?/td> 272K
代理商: 28F640J5
28F320J5/28F640J5
E
8
PRELIMINARY
Table 1. Lead Descriptions
(Continued)
Symbol
Type
Name and Function
BYTE#
INPUT
BYTE ENABLE:
BYTE# low places the device in x8 mode. All data is then input
or output on DQ
0
–DQ
7
, while DQ
8
–DQ
15
float. Address A
0
selects between the
high and low byte. BYTE# high places the device in x16 mode, and turns off the
A
0
input buffer. Address A
1
then becomes the lowest order address.
V
PEN
INPUT
ERASE / PROGRAM / BLOCK LOCK ENABLE:
For erasing array blocks,
programming data, or configuring lock-bits.
With V
PEN
V
PENLK
, memory contents cannot be altered.
V
CC
SUPPLY
DEVICE POWER SUPPLY:
With V
CC
V
LKO
, all write attempts to the flash
memory are inhibited.
V
CCQ
OUTPUT
BUFFER
SUPPLY
OUTPUT BUFFER POWER SUPPLY:
This voltage controls the device’s output
voltages. To obtain output voltages compatible with system data bus voltages,
connect V
CCQ
to the system supply voltage.
GND
SUPPLY
GROUND:
Do not float any ground pins.
NC
NO CONNECT:
Lead is not internally connected; it may be driven or floated.
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