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參數(shù)資料
| 型號(hào)： | 37C669 |
| 廠商： | SMSC Corporation |
| 英文描述： | DIODE SCHOTTKY SINGLE 25V 200mW 0.5V-vf 200mA-IFM 30mA-IF 2uA-IR SOD-323 3K/REEL |
| 中文描述： | 電腦98/99順從超級(jí)I / O軟盤控制器與紅外線支持 |
| 文件頁數(shù)： | 131/164頁 |
| 文件大小： | 621K |
| 代理商： | 37C669 |
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69
When both GAP and WGATE bits of the
PERPENDICULAR MODE COMMAND are both
programmed to "0" (Conventional mode), then
D0, D1, D2, D3, and D4 can be programmed
independently to "1" for that drive to be set
automatically to Perpendicular mode.
In this
mode the following set of conditions also apply:
1. The GAP2 written to a perpendicular drive
during a write operation will depend upon the
programmed data rate.
2. The write pre-compensation given to a
perpendicular mode drive wil be 0ns.
3. For
D0-D3
programmed
to
"0"
for
conventional mode drives any data written
will be at the currently programmed write
pre-compensation.
Note: Bits D0-D3 can only be overwritten when
OW is programmed as a "1".
If either GAP or WGATE is a "1" then
D0-D3 are ignored.
Software
and
hardware
resets
have
the
following
effect
on
the
PERPENDICULAR
MODE COMMAND:
1. "Software" resets (via the DOR or DSR
registers) will only clear GAP and WGATE
bits to "0". D0-D3 are unaffected and retain
their previous value.
2. "Hardware" resets will clear all bits (GAP,
WGATE
and
D0-D3)
to
"0",
i.e
all
conventional mode.
Table 29 - Effects of WGATE and GAP Bits
WGATE
GAP
MODE
LENGTH OF
GAP2 FORMAT
FIELD
PORTION OF
GAP 2
WRITTEN BY
WRITE DATA
OPERATION
0
1
0
1
0
1
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
22 Bytes
41 Bytes
0 Bytes
19 Bytes
0 Bytes
38 Bytes
LOCK
In order to protect systems with long DMA
latencies against older application software that
can disable the FIFO the LOCK Command has
been added.
This command should only be
used by the FDC routines, and application
software should refrain from using it.
If an
application calls for the FIFO to be disabled
then the CONFIGURE command should be
used.
The LOCK command defines whether the
EFIFO, FIFOTHR, and PRETRK parameters of
the CONFIGURE command can be RESET by
the DOR and DSR registers. When the LOCK
bit is set to logic "1" all subsequent "software
RESETS by the DOR and DSR registers will not
change the previously set parameters to their
default values. All "hardware" RESET from the
RESET pin will set the LOCK bit to logic "0" and
return the EFIFO, FIFOTHR, and PRETRK to
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