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參數(shù)資料
| 型號： | 37C669 |
| 廠商： | SMSC Corporation |
| 英文描述： | DIODE SCHOTTKY SINGLE 25V 200mW 0.5V-vf 200mA-IFM 30mA-IF 2uA-IR SOD-323 3K/REEL |
| 中文描述： | 電腦98/99順從超級I / O軟盤控制器與紅外線支持 |
| 文件頁數(shù)： | 156/164頁 |
| 文件大?。?/td> | 621K |
| 代理商： | 37C669 |
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91
BIT 0 STROBE - STROBE
This
bit
is
inverted
and
output
onto
the
nSTROBE output.
BIT 1 AUTOFD - AUTOFEED
This
bit
is
inverted
and
output
onto
the
nAUTOFD
output.
A
logic
1
causes
the
printer to generate a line feed after each line is
printed. A logic 0 means no autofeed.
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without
inversion.
BIT 3 SLCTIN - PRINTER SELECT INPUT
This bit is inverted and output onto the nSLCTIN
output. A logic 1 on this bit selects the printer; a
logic 0 means the printer is not selected.
BIT 4 IRQE - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a
high level may be used to enable interrupt
requests from the Parallel Port to the CPU. An
interrupt request is generated on the IRQ port by
a positive going nACK input. When the IRQE bit
is programmed low the IRQ is disabled.
BIT 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is valid in extended
mode only (CR#1<3>=0). In printer mode, the
direction is always out regardless of the state of
this bit. In bi-directional mode, a logic 0 means
that the printer port is in output mode (write); a
logic 1 means that the printer port is in input
mode (read).
Bits 6 and 7 during a read are a low level, and
cannot be written.
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of
'03H' from the base address.
The address
register is cleared at initialization by RESET.
During a WRITE operation, the contents of DB0-
DB7 are buffered (non inverting) and output onto
the PD0 - PD7 ports, the leading edge of nIOW
causes an EPP ADDRESS WRITE cycle to be
performed, the trailing edge of IOW latches
the data for the duration of the EPP write cycle.
During a READ operation, PD0 - PD7 ports are
read, the leading edge of IOR causes an EPP
ADDRESS READ cycle to be performed and the
data output to the host CPU, the deassertion of
ADDRSTB latches the PData for the duration of
the IOR cycle. This register is only available in
EPP mode.
EPP DATA PORT 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of
'04H' from the base address. The data register
is cleared at initialization by RESET. During a
WRITE operation, the contents of DB0-DB7 are
buffered (non inverting) and output onto the PD0
- PD7 ports, the leading edge of nIOW causes
an EPP DATA WRITE cycle to be performed,
the trailing edge of IOW latches the data for the
duration of the EPP write cycle. During a READ
operation, PD0 - PD7 ports are read, the leading
edge of IOR causes an EPP READ cycle to be
performed and the data output to the host CPU,
the deassertion of DATASTB latches the PData
for the duration of the IOR cycle. This register
is only available in EPP mode.
EPP DATA PORT 1/ADDRESS OFFSET = 05H
The EPP Data Port 1 is located at an offset of
'05H' from the base address.
Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP DATA PORT 2/ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of
'06H' from the base address.
Refer to EPP
DATA PORT 0 for a description of operation.
This register is only available in EPP mode.
EPP DATA PORT 3
ADDRESS OFFSET = 07H
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