參數(shù)資料
型號: 37C669
廠商: SMSC Corporation
英文描述: DIODE SCHOTTKY SINGLE 25V 200mW 0.5V-vf 200mA-IFM 30mA-IF 2uA-IR SOD-323 3K/REEL
中文描述: 電腦98/99順從超級I / O軟盤控制器與紅外線支持
文件頁數(shù): 2/164頁
文件大?。?/td> 621K
代理商: 37C669
10
DESCRIPTION OF PIN FUNCTIONS
QFP/
TQFP
PIN NO.
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
82,92
nClear to Send
nCTS1
nCTS2
I
Active low Clear to Send inputs for the serial
port.
Handshake signal which notifies the
UART that the modem is ready to receive
data.
The CPU can monitor the status of
nCTS signal by reading bit 4 of Modem
Status Register (MSR). A nCTS signal state
change from low to high after the last MSR
read will set MSR bit 0 to a 1. If bit 3 of
Interrupt Enable Register is set, the interrupt
is generated when nCTS changes state.
The nCTS signal has no effect on the
transmitter.
Note:
Bit 4 of MSR is the
complement of nCTS.
80,90
nData Set Ready nDSR1
nDSR2
I
Active low Data Set Ready inputs for the
serial port. Handshake signal which notifies
the UART that the modem is ready to
establish the communication link. The CPU
can monitor the status of nDSR signal by
reading bit 5 of Modem Status Register
(MSR). A nDSR signal state change from
low to high after the last MSR read will set
MSR bit 1 to a 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated
when nDSR changes state. Note: Bit 5 of
MSR is the complement of nDSR.
85,87
nData Carrier
Detect
nDCD1
nDCD2
I
Active low Data Carrier Detect inputs for the
serial port. Handshake signal which notifies
the UART that carrier signal is detected by
the modem.
The CPU can monitor the
status of nDCD signal by reading bit 7 of
Modem Status Register (MSR).
A nDCD
signal state change from low to high after
the last MSR read will set MSR bit 3 to a 1.
If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when nDCD
changes state. Note: Bit 7 of MSR is the
complement of nDCD.
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