參數(shù)資料
型號: 37C669
廠商: SMSC Corporation
英文描述: DIODE SCHOTTKY SINGLE 25V 200mW 0.5V-vf 200mA-IFM 30mA-IF 2uA-IR SOD-323 3K/REEL
中文描述: 電腦98/99順從超級I / O軟盤控制器與紅外線支持
文件頁數(shù): 36/164頁
文件大?。?/td> 621K
代理商: 37C669
130
CR10
This
register
can
only be accessed in the
Configuration Mode and after the CSR has been
initialized to 10H.
The default value of this
register after power up is 00H.
Table 58 - CR10
BIT NO.
BIT NAME
DESCRIPTION
0 - 2
Reserved
Reserved - READ ONLY. A read returns a 0.
3
Pll Gain
This bit controls the gain of the frequency multiplying phase lock
loops. When a 0 (default) the gain is set to a value expected for 5
volt operation. When set to a 1 the gain is doubled to a value for
possible 3 volt operation.
4
Pll Stop
A 1 in this bit position stops the frequency multiplying phase lock
loops. A 0 (default) allows normal operation.
5
ACE_STOP
This bit when set to a 1 will inhibit the 24MHz clock to the divide by
12/13 that generates the UART clocks, and reset those dividers.
When at a 0 (default) these dividers and clocks are enabled.
6
PLL Clock
Control
This bit enables the PLL clock generator to run with either a
14.318MHz or 24MHz input clock. A 0 enables the 14.318MHz clock
(default), a 1 enables the 24MHz clock.
7
Infra Red Test
This bit enables the IR test mode. When this bit is set to a 1 the
serial data seen by UART RX and TX ports is output on SOUT. A 0
gives normal operation (default).
CR11
This
register
can
only be accessed in the
Configuration Mode and after the CSR has
been initialized to 11H. The default value of this
register after power up is 00H.
Table 59 - CR11
BIT NO.
BIT NAME
DESCRIPTION
0
IR Loop Back
When a 1 the IROUT is looped back internally to the IRIN input.
When a 0 (default) normal operation.
1
Test 10ms
This bit when a 1 tests the 10ms timeout of the FDC autopower down
mode. A 0 (default) allows normal operation.
2 - 7
Reserved
Reserved - READ ONLY. A read returns a 0.
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