參數(shù)資料
型號(hào)： 37C957FR
廠商： SMSC Corporation
英文描述： ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS
中文描述： 超的I / O控制器的便攜式應(yīng)用
文件頁(yè)數(shù)： 165/328頁(yè)
文件大?。?/td> 1208K
代理商： 37C957FR
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241
PS/2 Device Interface
PS/2 Logic Overview
The FDC37C957FR has four PS/2 serial ports implemented in hardware which are directly controlled
by the on chip 8051.
The hardware implementation eliminates the need to bit bang I/O ports to
generate PS/2 ports. The PS/2 logic allows the host to communicate to any serial auxiliary devices
compatible with the PS/2 interface through any one of four ports : EM, KB, IM and PS2. There are
two identical PS/2 channels, each containing a set of five operating registers. Channel 1 (PS/2 Port
1) consists of ports EM and KB and channel 2 (PS/2 Port 2) consists of ports IM and PS2.
Each of the four PS/2 serial ports use a synchronous serial protocol to communicate with the auxiliary
device. Each PS/2 port has two signal lines : Clock and Data. Both signal lines are bi-directional and
imply open drain outputs. A pull-up resistor (typically 3.3K) is connected to the clock and data lines.
This allows either the FDC37C957FR PS/2 logic or the auxiliary device to control both lines.
Regardless, the auxiliary device provides the clock for transmit and receive operations. The serial
packet is made up of eleven bits, listed in order as they will appear on the data line : start bit, eight
data bits (least significant bit first), odd parity, and stop bit. Each bit cell is from 60
S to 100S long.
The data is latched on the high to low transition of the clock.
Transmitting to the Remote Auxiliary Device
The PS/2 serial protocol requires that the auxiliary device respond to all transmissions that it
receives. The response will either be an 0XFA or 0xEE. The response is stored in the PS/2 ports
RECEIVE register. Thus, after each transmission the RECEIVE register should contain either 0xFA
or 0xEE.
A port is set to transmit by selecting the port and enabling the transmitter. This is done by writing to the
CONTROL register. The PS/2 logic drives the clock line low and then floats the data line when the port is
selected to transmit. Writing to the TRANSMIT register initiates the transmit operation. The data line is
driven low and, within 80ns, the clock line is floated (externally pulled high by the pull-up resistor). The
auxiliary device recognizes this as the FDC37C957’s start bit, and responds by providing the eleven clocks
(each clock corresponds to a bit). The Logic provides a 3.2
S bit hold time. If the auxiliary device did not
respond within ___mS after the start bit, transmit is terminated and ERROR bit of the STATUS register and
the RTSTIMOUT bit of the ERROR register are set. The auxiliary device has ___
S to complete one bit
transmission or the FDC37C957’s PS/2 logic will set the ERROR bit
of the STATUS register and the
XMTTIMOUT bit of the ERROR register. If the transmission is successful, the clock and data lines are
floated waiting for the auxiliary device to send the response packet. If the response packet is not received
within ___mS, the ERROR bit of the STATUS register is set, the RESTIMOUT bit of the ERROR register is
set and the RECEIVE register content is set to 0xF7. If, on the other hand, the response packet is received
and there are no errors, the PS/2 logic sets the READY bit of the STATUS register, clears the ERROR bit of
the STATUS register, and clears the ERROR register.
The RECEIVE register contains the eceived
response byte.
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