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| 型號(hào)： | 37C957FR |
| 廠商： | SMSC Corporation |
| 英文描述： | ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS |
| 中文描述： | 超的I / O控制器的便攜式應(yīng)用 |
| 文件頁(yè)數(shù)： | 23/328頁(yè) |
| 文件大?。?/td> | 1208K |
| 代理商： | 37C957FR |
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113
EPP 1.9 OPERATION
When the EPP mode is selected in the configuration register, the standard and bi-directional modes
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is
in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by
the SPP Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed
from the start of the EPP cycle (nIOR or nIOW asserted) to nWAIT being deasserted (after
command).
If a time-out occurs, the current EPP cycle is aborted and the time-out condition is
indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to
always be in a write mode and the nWRITE signal to always be asserted.
Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic
"0" (i.e. a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1",
and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a
logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated.
EPP 1.9 Write
The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or
Address cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it
has been determined that the write cycle can complete.
The write cycle can complete under the
following circumstances:
1.
If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active
then the write can complete when nWAIT goes inactive high.
2.
If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low
before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once
nWAIT is determined inactive.
Write Sequence of operation
1.
The host selects an EPP register, places data on the SData bus and drives nIOW active.
2.
The chip drives IOCHRDY inactive (low).
3.
If WAIT is not asserted, the chip must wait until WAIT is asserted.
4.
The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.
5.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information,
and the WRITE signal is valid.
6.
Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the
chip may begin the termination phase of the cycle.
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| 37D-2-110-SL | 制造商:OENINDIA 制造商全稱(chēng):OEN India Limited 功能描述:ICE CUBE STYLE INDUSTRIAL RELAY |
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