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On exiting the reset state, various internal registers are cleared, including the Configure command
information, and the FDC waits for a new command. Drive polling will start unless disabled by a new
Configure command.
RESET_OUT Pin (Hardware Reset)
The RESET_OUT pin is a global reset and clears all registers except those programmed by the
Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset
state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same. Both will reset the FDC core, which affects drive status
information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset
requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR
reset is set automatically upon a RESET_OUT pin reset. The user must manually clear this reset bit
in the DOR to exit the reset state.
FDC MODES OF OPERATION
The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are
determined by the state of IDENT and MFM, bits[3] and [2] respectively of L0-CRF0.
PC/AT mode - (IDENT high, MFM a "don't care")
The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (The FDC’s IRQ
and DRQ can be hi-Z), and TC and DENSEL become active high signals.
PS/2 mode - (IDENT low, MFM high)
This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the
DOR becomes a "don't care", (The FDC’s IRQ and DRQ are always valid), TC and DENSEL become
active low.
Model 30 mode - (IDENT low, MFM low)
This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR
becomes valid (The FDC’s IRQ and DRQ can be hi-Z), TC is active high and DENSEL is active low.
DMA TRANSFERS
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating its
DRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and
addresses need not be valid.
Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read
is performed by the FDC based only on nDACK. This mode is only available when the FDC has
been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO